16.4.5. Conditional instructions

Because the processor is statically scheduled, it schedules conditional instructions on the basis that they pass their condition codes. This means multi-cycle instructions such as LDM and STM instructions can still complete all their iterations even if they fail their condition codes.

An additional point about conditional instructions is that the destination register of the instruction is treated as an additional source operand. This is done so the old value can be forwarded in the case when the instruction fails the condition codes. This additional source operand is required in the E2 stage of the machine.

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