Using this manual

This manual is organized into the following chapters:

Chapter 1 Introduction

Read this for an introduction to the processor and descriptions of the major functional blocks.

Chapter 2 Programmers Model

Read this for a description of the processor registers and programming details.

Chapter 3 System Control Coprocessor

Read this for a description of the system control coprocessor CP15 registers and programming information.

Chapter 4 Unaligned Data and Mixed-endian Data Support

Read this for a description of the processor support for unaligned and mixed-endian data accesses. It also describes Advanced Single Instruction Multiple Data (SIMD) data access and alignment.

Chapter 5 Program Flow Prediction

Read this for a description of branch prediction, including guidelines for optimal performance, and how to enable program flow prediction.

Chapter 6 Memory Management Unit

Read this for a description of the Memory Management Unit (MMU) and the address translation process, including a list of CP15 registers that control the MMU.

Chapter 7 Level 1 Memory System

Read this for a description of the Level 1 memory system that consists of separate instruction and data caches.

Chapter 8 Level 2 Memory System

Read this for a description of the Level 2 memory system, including the L2 PreLoad Engine (PLE).

Chapter 9 External Memory Interface

Read this for a description of the external memory interface including AXI control signals in the processor.

Chapter 10 Clock, Reset, and Power Control

Read this for a description of the clocking modes and the reset signals. This chapter also describes the power control facilities that include the different clock gating levels to control power and skew.

Chapter 11 Design for Test

Read this for a description of the Design For Test (DFT) features of the processor.

Chapter 12 Debug

Read this for a description of the debug support.

Chapter 13 NEON and VFP Programmers Model

Read this for an overview of the NEON and Vector Floating-Point (VFP) coprocessor and a description of the NEON and VFP registers and programming details.

Chapter 14 Embedded Trace Macrocell

Read this for an overview of the Embedded Trace Macrocell (ETM).

Chapter 15 Cross Trigger Interface

Read this for a description of the Cross Trigger Interface (CTI).

Chapter 16 Instruction Cycle Timing

Read this for a description of the instruction cycle timing and for details of the interlocks.

Chapter 17 AC Characteristics

Read this for a description of the timing parameters applicable to the processor.

Appendix A Signal Descriptions

Read this for a summary of the processor signals.

Appendix B Instruction Mnemonics

Read this for a list of the Unified Assembler Language (UAL) equivalents of the legacy Advanced SIMD data-processing and VFP data-processing assembly language mnemonics used in this manual.

Appendix C Revisions

Read this for a list of the technical changes between released issues of this book.

Glossary

Read the Glossary for definitions of terms used in this manual.

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