3.2.42. c9, Performance Monitor Control Register

The purpose of the Performance MoNitor Control (PMNC) Register is to control the operation of the four Performance Monitor Count Registers, and the Cycle Counter Register:

The PMNC Register is:

Figure 3.38 shows the bit arrangement of the PMNC Register.

Figure 3.38. Performance Monitor Control Register format

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Table 3.82 shows how the bit values correspond with the PMNC Register functions.

Table 3.82. Performance Monitor Control Register bit functions

BitsFieldFunction

[31:24]

IMP

Specifies the implementor code:

0x41 = ARM.

[23:16]

IDCODE

Specifies the identification code:

0x0.

[15:11]

N

Specifies the number of counters implemented:

0x4 = 4 counters implemented.

[10:6]

-

Reserved. RAZ, SBZP.

[5]

DP

Disables cycle counter, CCNT, when non-invasive debug is prohibited:

0 = count is enabled in regions where non-invasive debug is prohibited

1 = count is disabled in regions where non-invasive debug is prohibited.

[4]

X

Enables export of the events from the event bus to an external monitoring block, such as the ETM to trace events:

0 = export disabled, reset value

1 = export enabled.

[3]

D

Cycle count divider:

0 = counts every processor clock cycle, reset value

1 = counts every 64th processor clock cycle.

[2]

C

Cycle counter reset:

0 = no action

1 = resets cycle counter, CCNT, to zero.

This bit Read-As-Zero.

[1]

P

Performance counter reset:

0 = no action

1 = resets all performance counters to zero.

This bit Read-As-Zero.

[0]

E

Enable bit:

0 = disables all counters, including CCNT

1 = enables all counters including CCNT.


The PMNC Register is always accessible in privileged modes. Table 3.83 shows the results of attempted access for each mode.

Table 3.83. Results of access to the Performance Monitor Control Register[34]

EN[a]

Secure privileged

Nonsecure privileged

Secure User

Nonsecure User

ReadWriteReadWriteReadWriteReadWrite
0

Data

DataDataData

Undefined

Undefined

Undefined

Undefined

1DataDataDataDataDataDataDataData

[34] An entry of Undefined in the table means that the access gives an Undefined Instruction exception when the coprocessor instruction is executed.

[a] The EN bit in c9, User Enable Register enables User mode access of the Performance Monitor Registers.


To access the PMNC Register, read or write CP15 with:

MRC p15, 0, <Rd>, c9, c12, 0 ; Read PMNC Register
MCR p15, 0, <Rd>, c9, c12, 0 ; Write PMNC Register
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