Cortex-A8 Technical Reference Manual: 3.2.1. Register allocation

3.2.1. Register allocation

Table 3.3 shows a summary the register allocation and reset values of the system control coprocessor where:

CRn is the register number within CP15
Op1 is the Opcode_1 value for the register
CRm is the operational register
Op2 is the Opcode_2 value for the register
Security state can be Secure, S, or Nonsecure, NS, and is:
- B, registers banked in Secure and Nonsecure states. If the registers are not banked then they are common to Secure or Nonsecure states or only accessible in one state.
- NA, no access
- RO, read-only access
- RO, read-only access in privileged modes only
- R/W, read/write access
- R/W, read/write access in privileged modes only
- WO, write-only access
- WO, write-only access in privileged modes only
- X, access depends on another register or external signal.

Table 3.3. Summary of CP15 registers and operations

CRn	Op1	CRm	Op2	Register or operation	Security state		Reset value	Page
					NS	S
c0	0	c0	{0, 4, 6-7}	Main ID	RO	RO	`0x413FC082`	c0, Main ID Register
			1	Cache Type	RO	RO	`0x82048004`	c0, Cache Type Register
			2	TCM Type	RO	RO	`0x00000000`	c0, TCM Type Register
			3	TLB Type	RO	RO	`0x00202001`	c0, TLB Type Register
			5	Multiprocessor ID	RO	RO	`0x00000000`	c0, Multiprocessor ID Register
		c1	0	Processor Feature 0	RO	RO	`0x00001131`	c0, Processor Feature Register 0
			1	Processor Feature 1	RO	RO	`0x00000011`	c0, Processor Feature Register 1
			2	Debug Feature 0	RO	RO	`0x00010400` or `0x00000400`	c0, Debug Feature Register 0
			3	Auxiliary Feature 0	RO	RO	`0x00000000`	c0, Auxiliary Feature Register 0
			4	Memory Model Feature 0	RO	RO	`0x01100003`	c0, Memory Model Feature Register 0
			5	Memory Model Feature 1	RO	RO	`0x20000000`	c0, Memory Model Feature Register 1
			6	Memory Model Feature 2	RO	RO	`0x01202000`	c0, Memory Model Feature Register 2
			7	Memory Model Feature 3	RO	RO	`0x00000211`	c0, Memory Model Feature Register 3
		c2	0	Instruction Set Attribute 0	RO	RO	`0x00101111`	c0, Instruction Set Attributes Register 0
			1	Instruction Set Attribute 1	RO	RO	`0x13112111`	c0, Instruction Set Attributes Register 1
			2	Instruction Set Attribute 2	RO	RO	0x21232031	c0, Instruction Set Attributes Register 2
			3	Instruction Set Attribute 3	RO	RO	`0x11112131`	c0, Instruction Set Attributes Register 3
			4	Instruction Set Attribute 4	RO	RO	`0x00011142`	c0, Instruction Set Attributes Register 4
			5-7	Instruction Set Attribute 5-7	RO	RO	`0x00000000`	c0, Instruction Set Attributes Registers 5-7
		c3-c7	0-7	Reserved for Feature ID Registers	RO	RO	`0x00000000`	-
		c8-c15	0-7	Undefined	-	-	-	-
	1	c0	0	Cache Size Identification	RO	RO	Unpredictable	c0, Cache Size Identification Registers
			1	Cache Level ID	RO	RO	`0x0A000023` or `0x0A000003`	c0, Cache Level ID Register
			2-6	Undefined	-	-	-	-
			7	Silicon ID	RO	RO	^[a]	c0, Silicon ID Register
		c1-c15	0-7	Undefined	-	-	-	-
	2	c0	0	Cache Size Selection	R/W	R/W, B	Unpredictable	c0, Cache Size Selection Register
		c0	1-7	Undefined	-	-	-	-
		c1-c15	0-7	Undefined	-	-	-	-
	3-7	c0-c15	0-7	Undefined	-	-	-	-
c1	0	c0	0	Control	R/W	R/W, B^[b], X	`0x00C50078`^[c]	c1, Control Register
			1	Auxiliary Control	B	B	`0x00000002`	c1, Auxiliary Control Register
			2	Coprocessor Access Control	R/W	R/W	`0x00000000`	c1, Coprocessor Access Control Register
			3-7	Undefined	-	-	-	-
		c1	0	Secure Configuration	NA	R/W	`0x00000000`	c1, Secure Configuration Register
			1	Secure Debug Enable	NA	R/W	`0x00000000`	c1, Secure Debug Enable Register
			2	Nonsecure Access Control	RO	R/W	`0x00000000`	c1, Nonsecure Access Control Register
			3-7	Undefined	-	-	-	-
		c2-c15	0-7	Undefined	-	-	-	-
	1-7	c0-c15	0-7	Undefined	-	-	-	-
c2	0	c0	0	Translation Table Base 0	R/W	R/W, B, X	Unpredictable	c2, Translation Table Base Register 0
			1	Translation Table Base 1	R/W	R/W, B	Unpredictable	c2, Translation Table Base Register 1
			2	Translation Table Base Control	R/W	R/W, B, X	Unpredictable	c2, Translation Table Base Control Register
			3-7	Undefined	-	-	-	-
		c1-c15	0-7	Undefined	-	-	-	-
	1-7	c0-c15	0-7	Undefined	-	-	-	-
c3	0	c0	0	Domain Access Control	R/W	R/W, B, X	Unpredictable	c3, Domain Access Control Register
			1-7	Undefined	-	-	-	-
		c1-c15	0-7	Undefined	-	-	-	-
	1-7	c0-c15	0-7	Undefined	-	-	-	-
c4	0-7	c0-c15	0-7	Undefined	-	-	-	-
c5	0	c0	0	Data Fault Status	R/W	R/W, B	Unpredictable	c5, Data Fault Status Register
			1	Instruction Fault Status	R/W	R/W, B	Unpredictable	c5, Instruction Fault Status Register
			2-7	Undefined	-	-	-	-
		c1	0	Data Auxiliary Fault Status	R/W	R/W, B	Unpredictable	c5, Auxiliary Fault Status Registers
			1	Instruction Auxiliary Fault Status	R/W	R/W, B	Unpredictable	c5, Auxiliary Fault Status Registers
		c1	2-7	Undefined	-	-	-	-
		c2-c15	0-7	Undefined	-	-	-	-
	1-7	c0-c15	0-7	Undefined	-	-	-	-
c6	0	c0	0	Data Fault Address	R/W	R/W, B	Unpredictable	c6, Data Fault Address Register
			1	Undefined	-	-	-	-
			2	Instruction Fault Address	R/W	R/W, B	Unpredictable	c6, Instruction Fault Address Register
			3-7	Undefined	-	-	-	-
		c1-c15	0-7	Undefined	-	-	-	-
	1-7	c0-c15	0-7	Undefined	-	-	-	-
c7	0	c0	0-3	Undefined	-	-	-	-
			4	NOP (WFI)	WO	WO	-	About the system control coprocessor
			5-7	Undefined	-	-	-	-
		c1-c3	0-7	Undefined	-	-	-	-
		c4	0	Physical Address	R/W	R/W, B	`0x00000000`	PA Register
			1-7	Undefined	-	-	-	-
		c5	0	Invalidate all instruction caches to point of unification	WO	WO	-	c7, Cache operations
			1	Invalidate instruction cache line to point of unification	WO	WO	-	c7, Cache operations
			2-3	Undefined	-	-	-	-
			4	Flush Prefetch Buffer	WO	WO	-	c7, Cache operations
			5	Undefined	-	-	-	-
			6	NOP (Invalidate entire branch predictor array)	WO	WO	-	About the system control coprocessor
			7	NOP (Invalidate branch predictor array line by MVA)	WO	WO	-	About the system control coprocessor
		c6	0	Undefined	-	-	-	-
			1	Invalidate data cache line to point of coherency by MVA	WO	WO	-	c7, Cache operations
			2	Invalidate data cache line by set and way	WO	WO	-	c7, Cache operations
			3-7	Undefined	-	-	-	-
		c7	0-7	Undefined	-	-	-	-
		c8	0-3	VA to PA translation in the current state	WO	WO	-	VA to PA translation in the current Secure or Nonsecure state
			4-7	VA to PA translation in the other state	NA	WO	-	VA to PA translation in the other Secure or Nonsecure state
		c9	0-7	Undefined	-	-	-	-
		c10	0	Undefined	-	-	-	-
			1	Clean data cache line to point of coherency by MVA	WO	WO	-	c7, Cache operations
			2	Clean data cache line by set and way	WO	WO	-	c7, Cache operations
			3	Undefined	-	-	-	-
			4	Data Synchronization Barrier	WO	WO	-	Data synchronization barrier operation
			5	Data Memory Barrier	WO	WO	-	Data memory barrier operation
			6-7	Undefined	-	-	-	-
		c11	0	Undefined	-	-	-	-
			1	Clean data cache line to point of unification by MVA	WO	WO	-	c7, Cache operations
			2-7	Undefined	-	-	-	-
		c12-c13	0-7	Undefined	-	-	-	-
		c14	0	Undefined	-	-	-	-
			1	Clean and invalidate data cache line to point of coherency by MVA	WO	WO	-	c7, Cache operations
			2	Clean and invalidate data cache line by set and way	WO	WO	-	c7, Cache operations
			3-7	Undefined	-	-	-	-
		c15	0-7	Undefined	-	-	-	-
	1-7	c0-c15	0-7	Undefined	-	-	-	-
c8	0	c0-c4	0-7	Undefined	-	-	-	-
		c5	0	Invalidate Instruction TLB unlocked entries	WO	WO, B	-	c8, TLB operations
			1	Invalidate Instruction TLB entry by MVA	WO	WO, B	-	c8, TLB operations
			2	Invalidate Instruction TLB entry on ASID match	WO	WO, B	-	c8, TLB operations
			3-7	Undefined	-	-	-	-
		c6	0	Invalidate Data TLB unlocked entries	WO	WO, B	-	c8, TLB operations
			1	Invalidate Data TLB entry by MVA	WO	WO, B	-	c8, TLB operations
			2	Invalidate Data TLB entry on ASID match	WO	WO, B	-	c8, TLB operations
			3-7	Undefined	-	-	-	-
		c7	0	Invalidate unified TLB unlocked entries	WO	WO, B	-	c8, TLB operations
			1	Invalidate unified TLB entry by MVA	WO	WO, B	-	c8, TLB operations
			2	Invalidate unified TLB entry on ASID match	WO	WO, B	-	c8, TLB operations
			3-7	Undefined	-	-	-	-
		c8-c15	0-7	Undefined	-	-	-	-
	1-7	c0-c15	0-7	Undefined	-	-	-	-
c9	0	c0-c11	0-7	Undefined	-	-	-	-
		c12	0	Performance Monitor Control	R/W, X	R/W, X	`0x41002000`	c9, Performance Monitor Control Register
			1	Count Enable Set	R/W, X	R/W, X	`0x00000000`	c9, Count Enable Set Register
			2	Count Enable Clear	R/W, X	R/W, X	`0x00000000`	c9, Count Enable Clear Register
			3	Overflow Flag Status	R/W, X	R/W, X	`0x00000000`	c9, Overflow Flag Status Register
			4	Software Increment	R/W, X	R/W, X	`0x00000000`	c9, Software Increment Register
			5	Performance Counter Selection	R/W, X	R/W, X	Unpredictable	c9, Performance Counter Selection Register
			6-7	Undefined	-	-	-	-
		c13	0	Cycle Count	R/W, X	R/W, X	`0x00000000`	c9, Cycle Count Register
			1	Event Selection	R/W, X	R/W, X	Unpredictable	c9, Event Selection Register
			2	Performance Monitor Count	R/W, X	R/W, X	`0x00000000`	c9, Performance Monitor Count Registers
			3-7	Undefined	-	-	-	-
		c14	0	User Enable	R/W	R/W	`0x00000000`	c9, User Enable Register
			1	Interrupt Enable Set	R/W	R/W	`0x00000000`	c9, Interrupt Enable Set Register
			2	Interrupt Enable Clear	R/W	R/W	`0x00000000`	c9, Interrupt Enable Clear Register
			3-7	Undefined	-	-	-	-
		c15	0-7	Undefined	-	-	-	-
	1	c0	0	L2 Cache Lockdown	R/W	R/W	`0x00000000`	c9, L2 Cache Lockdown Register
			1	Undefined	-	-	-	-
			2	L2 Cache Auxiliary Control	RO	R/W	`0x00000042`	c9, L2 Cache Auxiliary Control Register
			3-7	Undefined	-	-	-	-
		c1-c15	0-7	Undefined	-	-	-	-
	2-7	c0-c15	0-7	Undefined	-	-	-	-
c10	0	c0	0	Data TLB Lockdown Register	R/W	R/W	`0x00000000`	c10, TLB Lockdown Registers
			1	Instruction TLB Lockdown Register	R/W	R/W	`0x00000000`	c10, TLB Lockdown Registers
			2-7	Undefined	-	-	-	-
		c1	0	Data TLB Preload	WO	WO	-	c10, TLB preload operation
			1	Instruction TLB Preload	WO	WO	-	c10, TLB preload operation
			2-7	Undefined	-	-	-	-
		c2	0	Primary Region Remap Register	R/W	R/W, B, X	`0x00098AA4`	c10, Memory Region Remap Registers
			1	Normal Memory Remap Register	R/W	R/W, B, X	`0x44E048E0`	c10, Memory Region Remap Registers
			2-7	Undefined	-	-	-	-
		c3-c15	0-7	Undefined	-	-	-	-
	1-7	c0-c15	0-7	Undefined	-	-	-	-
c11	0	c0	0	PLE Identification and Status	RO, X	RO	`0x00000003`^[d]	c11, PLE Identification and Status Registers
			1	Undefined	-	-	-	-
			2-3	PLE Identification and Status	RO, X	RO	`0x00000000`^[d]	c11, PLE Identification and Status Registers
			4-7	Undefined	-	-	-	-
		c1	0	PLE User Accessibility	R/W, X	R/W	`0x00000000`	c11, PLE User Accessibility Register
			1-7	Undefined	-	-	-	-
		c2	0	PLE Channel Number	R/W, X	R/W, X	Unpredictable	c11, PLE Channel Number Register
			1-7	Undefined	-	-	-	-
		c3	0-2	PLE enable	WO, X	WO, X	-	c11, PLE enable commands
			3-7	Undefined	-	-	-	-
		c4	0	PLE Control	R/W, X	R/W, X	Unpredictable	c11, PLE Control Register
			1-7	Undefined	-	-	-	-
		c5	0	PLE Internal Start Address	R/W, X	R/W, X	Unpredictable	c11, PLE Internal Start Address Register
			1-7	Undefined	-	-	-	-
		c6	0-7	Undefined	-	-	-	-
		c7	0	PLE Internal End Address	R/W, X	R/W, X	Unpredictable	c11, PLE Internal End Address Register
			1-7	Undefined	-	-	-	-
		c8	0	PLE Channel Status	RO, X	RO, X	`0x00000000`	c11, PLE Channel Status Register
			1-7	Undefined	-	-	-	-
		c9-14	0-7	Undefined	-	-	-	-
		c15	0	PLE Context ID	R/W, X	R/W	Unpredictable	c11, PLE Context ID Register
c11	0	c15	1-7	Undefined	-	-	-	-
	1-7	c0-c15	0-7	Undefined	-	-	-	-
c12	0	c0	0	Secure or Nonsecure Vector Base Address	R/W	R/W, B, X	`0x00000000`	c12, Secure or Nonsecure Vector Base Address Register
			1	Monitor Vector Base Address	NA	R/W, X	`0x00000000`	c12, Monitor Vector Base Address Register
			2-7	Undefined	-	-	-	-
		c1	0	Interrupt Status	RO	RO	`0x00000000`^[e]	c12, Interrupt Status Register
			1-7	Undefined	-	-	-	-
		c2-15	0-7	Undefined	-	-	-	-
	1-7	c0-15	0-7	Undefined	-	-	-	-
c13	0	c0	0	FCSE PID	R/W	R/W, B, X	`0x00000000`	c13, FCSE PID Register
			1	Context ID	R/W	R/W, B	Unpredictable	c13, Context ID Register
			2	User read/write Thread and Process ID	R/W	R/W, B	Unpredictable	c13, Thread and Process ID Registers
			3	User read-only Thread and Process ID	R/W, RO	R/W, RO, B^[f]	Unpredictable	c13, Thread and Process ID Registers
			4	Privileged only Thread and Process ID	R/W	R/W, B	Unpredictable	c13, Thread and Process ID Registers
			5-7	Undefined	-	-	-	-
		c1-c15	0-7	Undefined	-	-	-	-
	1-7	c0-c15	0-7	Undefined	-	-	-	-
c14	0-7	c0-c15	0-7	Undefined	-	-	-	-
c15	0	c0	0	D-L1 Data 0 Register	NA	R/W	Unpredictable	c15, L1 system array debug data registers
			1	D-L1 Data 1 Register	NA	R/W	Unpredictable	c15, L1 system array debug data registers
			2	D-TLB CAM write operation	NA	WO	-	c15, L1 TLB operations
			3	D-TLB ATTR write operation	NA	WO	-	c15, L1 TLB operations
			4	D-TLB PA write operation	NA	WO	-	c15, L1 TLB operations
			5	D-HVAB write operation	NA	WO	-	c15, L1 HVAB array operations
			6	D-Tag write operation	NA	WO	-	c15, L1 tag array operations
			7	D-Data write operation	NA	WO	-	c15, L1 data array operations
		c1	0	I-L1 Data 0 Register	NA	R/W	Unpredictable	c15, L1 system array debug data registers
			1	I-L1 Data 1 Register	NA	R/W	Unpredictable	c15, L1 system array debug data registers
			2	I-TLB CAM write operation	NA	WO	-	c15, L1 TLB operations
			3	I-TLB ATTR write operation	NA	WO	-	c15, L1 TLB operations
			4	I-TLB PA write operation	NA	WO	-	c15, L1 TLB operations
			5	I-HVAB write operation	NA	WO	-	c15, L1 HVAB array operations
			6	I-Tag write operation	NA	WO	-	c15, L1 tag array operations
			7	I-Data write operation	NA	WO	-	c15, L1 data array operations
		c2	0-1	Undefined	-	-	-	-
			2	D-TLB CAM read operation	NA	WO	-	c15, L1 TLB operations
			3	D-TLB ATTR read operation	NA	WO	-	c15, L1 TLB operations
			4	D-TLB PA read operation	NA	WO	-	c15, L1 TLB operations
			5	D-HVAB read operation	NA	WO	-	c15, L1 HVAB array operations
			6	D-Tag read operation	NA	WO	-	c15, L1 tag array operations
			7	D-Data read operation	NA	WO	-	c15, L1 data array operations
		c3	0-1	Undefined	NA	-	-	-
			2	I-TLB CAM read operation	NA	WO	-	c15, L1 TLB operations
			3	I-TLB ATTR read operation	NA	WO	-	c15, L1 TLB operations
			4	I-TLB PA read operation	NA	WO	-	c15, L1 TLB operations
			5	I-HVAB read operation	NA	WO	-	c15, L1 HVAB array operations
			6	I-Tag read operation	NA	WO	-	c15, L1 tag array operations
			7	I-Data read operation	NA	WO	-	c15, L1 data array operations
		c4	0-7	Undefined	-	-	-	-
		c5	0-1	Undefined	-	-	-	-
			2	GHB write operation	NA	WO	-	c15, GHB array operations
			3	BTB write operation	NA	WO	-	c15, BTB array operations
			4-7	Undefined	-	-	-	-
		c6	0-7	Undefined	-	-	-	-
		c7	0-1	Undefined	-	-	-	-
			2	GHB read operation	NA	WO	-	c15, GHB array operations
			3	BTB read operation	NA	WO	-	c15, BTB array operations
			4-7	Undefined	-	-	-	-
		c8	0	L2 Data 0 Register	NA	R/W	Unpredictable	c15, L2 system array debug data registers
			1	L2 Data 1 Register	NA	R/W	Unpredictable	c15, L2 system array debug data registers
			2	L2 tag, L2 valid write operation	NA	WO	-	c15, L2 tag array operations
			3	L2 data, L2 dirty write operation	NA	WO	-	c15, L2 tag array operations
			4	L2 parity and ECC write operation	NA	WO	-	c15, L2 parity/ECC array operations
			5	L2 Data 2 Register	NA	R/W	Unpredictable	c15, L2 system array debug data registers
			6-7	Undefined	-	-	-	-
		c9	0-1	Undefined	-	-	-	-
			2	L2 tag, L2 valid read operation	NA	WO	-	c15, L2 tag array operations
			3	L2 data, L2 dirty read operation	NA	WO	-	c15, L2 tag array operations
			4	L2 parity and ECC read operation	NA	WO	-	c15, L2 parity/ECC array operations
			5-7	Undefined	-	-	-	-
		c10-c15	0-7	Undefined	-	-	-	-
	1-7	c0-c15	0-7	Undefined	-	-	-	-
^[a]Reset value depends on external signals, that is, SILICONID[31:0]. ^[b]Some bits in this register are banked and some are secure modify only. ^[c]Reset value depends on external signals, that is, VINITHI, CFGTE, and CFGNMFI. The value shown in this table assumes these signals are set to zero. ^[d]Reset value depends on the number of PLE channels implemented. ^[e]Reset value depends on external signals, that is, nFIQ and nIRQ. The value shown in this table assumes these signals are set to zero. ^[f]This register is read/write in privileged modes and read-only in User mode.

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