The address channel timing diagrams are provided in:
The diagrams provided in Figure 2.10 and Figure 2.11 illustrate the timing for the write address
channel. The timing for the read address channel is the same as
that shown for these figures. The signal name prefixes change from AW to AR.
Figure 2.10 shows
the write address channel for a transaction with zero latency. This zero
latency is because the address channel arbiter has already granted
the master.
Figure 2.11 shows
the write address channel for a transaction with latency. The one cycle
latency at T1-T2 for AWVALIDSx and AWVALIDMx is caused by the address arbiter
switching from the old master to the new one.
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