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You can configure the options described in:
You can specify the number of master and slave interfaces that the interconnect is built with. There is no limit on the number of masters or slaves that the interconnect can support although you must be aware of the timing implications of a matrix with a large number of interfaces.
The ACI supports the AXI bus protocol with either 32-bit or 64-bit data paths. If you require a mix of data widths then you can integrate standard components such as the AXI Downsizer to the periphery of the interconnect to provide the necessary data width conversion. See the PrimeCell Infrastructure AMBA 3 AXI Downsizer (BP131) Technical Overview for more information.
You can configure the ID width of each slave interface to a defined width. This enables you to connect masters with different ID widths. If the slave interface has an ID width of zero then the slave interface Verilog is configured to have zero ID ports.
The width of the master interface ID on the interconnect is not configurable. It is a function of the maximum slave interface ID width and the number of slave interfaces on the interconnect.
Figure 2.1 illustrates this with an example. It shows an interconnect with two masters:
slave interface?0 has a configured ID width of two bits
slave interface?1 has a configured ID width of four bits.
The master interface in Figure 2.1 has an ID width of five bits. This is derived automatically from the calculation:
(largest slave interface ID width) + (log2(total number of slave interfaces)).
You must configure your slaves to match the derived interconnect master interface ID width.
The interconnect appends bits to the ID to differentiate between the physical masters in the system. If necessary, the interconnect pads the incoming ID to equal the width of the master interface automatically.
For example, if master M1 in Figure 2.1 accesses slave S0 with an ID value of b1001 then one bit with a value of 1 is added to the slave interface ID least significant bit to indicate that this is from master M1. Therefore the slave receives a 5 bit ID with a value of b10011.
Another example is if master M0 in Figure 2.1 accesses slave S0 with an ID value of b11 then one bit with a value of 0 is added to the slave interface ID least significant bit to indicate that this is from master M0. Two bits with a value of b00 are also added to the slave interface ID most significant bit to pad the ID width to 5 bits. Therefore the slave receives a 5 bit ID with a value of b00110.
You can configure the maximum number of active read transactions a slave interface can accept. You are advised to set the read acceptance capability of the slave interface to match the read issuing capability of its attached master interface.
Similarly you can configure the maximum number of active write transactions a slave interface can accept. You are advised to set the write acceptance capability of the slave interface to match the write issuing capability of its attached master interface.
In any interconnect that is connected to a slave that reorders read data or write response signals, there is the potential for deadlock. To prevent this the ACI provides three cyclic dependency schemes that enables the slave interface to accept or stall a new transaction address. Each slave interface can be configured to one of the following cyclic dependency schemes:
Single Slave
Unique ID
Hybrid
Each of these schemes are described in more detail in the following sections.
In this configuration the ACI implements a deadlock prevention scheme that accepts or stalls a new transaction address based on the following rules:
A master can initiate a transaction to any slave if the master has no outstanding transactions.
If the master does have outstanding transactions then:
a master can initiate a transaction to the same slave as the current outstanding transactions.
Figure 2.2 shows these rules.
This scheme adds minimal logic to the ACI interconnect, so this option has the least timing impact although it does not provide the flexibility of the two other schemes.
In this configuration the ACI implements a deadlock prevention scheme that accepts or stalls a new transaction address based on the following rules:
A master can initiate a transaction to any slave if the master has no outstanding transactions.
If the master does have outstanding transactions then:
a master can initiate a transaction to any slave but only if the transaction ID of the current transaction is unique, relative to current outstanding transactions.
The unique ID scheme can only be used when the slave interface ID width is greater than 0.
Figure 2.3 shows these rules.
This scheme adds additional logic to the ACI interconnect, so this option provides a compromise between timing impact and transaction handling. The PrimeCell AXI Configurable Interconnect (PL300) Implementation Guide describes how to choose the appropriate cyclic dependency scheme.
In this configuration the ACI implements a deadlock prevention scheme that accepts or stalls a new transaction address based on the following rules:
A master can initiate a transaction to any slave if the master has no outstanding transactions
If the master does have outstanding transactions then:
a master can initiate a transaction to the same slave as the current outstanding transactions, or
a master can initiate a transaction to any slave but only if the transaction ID of the current transaction is unique, relative to current outstanding transactions.
The hybrid scheme can only be used when the slave interface ID width is greater than 0.
Figure 2.4 shows these rules.
This scheme adds the greatest logic to the ACI interconnect, so this option has the most timing impact but it does provide the greatest flexibility in handling transactions compared with the two previous schemes.
You can configure the number of outstanding write addresses that each interconnect master interface is capable of issuing. You are advised to set the master interface write issuing capability to match the write acceptance capability of its attached slave.
Out-of-order data is supported for read and write data as described in:
Write data interleaving enables the interconnect to combine write data streams from different physical masters, to a single slave. This is useful because you can combine write data from a fast master with write data from a slow master and consequently increase the throughput of data across the interconnect.
The ACI supports write data interleaving and you can configure each master interface to support a slave with a different write interleave depth (see theGlossary). For slaves with an interleave depth of greater than one, such as the PrimeCell Dynamic Memory Controller (PL340), the interconnect can interleave write data from a number of different physical masters to maximize write data throughput and minimize latency for a given master.
Interconnect slave interfaces have a fixed non-configurable write interleave depth of one. A connected master must not interleave write data to that interface and therefore its write interleaving capability must be equal to one.
You cannot interleave write data through cascaded interconnects. If you are using cascaded interconnects then you must ensure that the write interleaving capability of any master interface that connects to an interconnect slave interface is set to 1.
As an example, Figure 2.5 shows an interconnect with two masters and one slave. The configured write interleave capability of master interface 0 is set at two to match the write interleave depth of slave 0.
Assuming master 1 is capable of transmitting data faster than master 0, then Figure 2.6 shows the relative interleaved write transactions from master 0 and master 1 to slave 0.
In Figure 2.6:
Signifies write address accepted.
Signifies write data.
Signifies the write response.
Figure 2.6 shows that write data from master 1 is interleaved with write data from master 0. This decreases the time for both write transactions to complete.
The ACI supports slaves that are capable of reordering read data. You do not have to configure the interconnect to support this feature.
A read transaction tracking scheme is implemented to ensure that each master is permitted to have outstanding read transactions to a single slave only. This ensures that deadlock does not occur in the interconnect when slaves reorder read data.
The ACI allows you to define a memory map that assigns how the slaves are decoded. Each memory region is permitted to be non-contiguous.
You can use REMAP signals to switch dynamically between any number of pre-configured memory maps. See the PrimeCell AXI Configurable Interconnect (PL300) Implementation Guide for more information.
The interconnect provides a decode error response, DECERR, for any areas in the memory map that are not assigned to any slave.
An internal default slave is included in the design. When any slave attempts to access an area of memory that is undefined then the transfer is routed to the default slave. This accepts the transaction and returns a DECERR in either:
RRESP for a read
BRESP for a write. The entire WDATA burst is accepted normally for a write and it is only in the write response that the master is informed that there is an error.
Each address channel has a separate decoder so that read and
write addresses can be accepted simultaneously. Each decoder uses
the same memory map. The created HDL for the decoder block is partitioned
into a separate file, pl300_DecodeScheme_<name>.v,
to enable you to modify the RTL in the unlikely event that the XML
memory map options do not meet your requirements. See the PrimeCell
AXI Configurable Interconnect (PL300) Implementation Guide for
more information and examples.
| Copyright © 2004-2005 ARM Limited. All rights reserved. | ARM DDI 0354B |
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| PDF version | |
| Home > Functional Overview > Functional description > Configurable interconnect options |