C.5.3. MBIST dispatch unit and MPCore signals
Table C.5 shows
the MBIST dispatch unit signals.
Table C.5. MBIST dispatch unit signals
| Name | Direction | Description |
|---|
| MTESTON | Input | Switches multiplexers to give access to the
RAMs. Must be HIGH during MBIST mode. |
| MBISTDIN[63:0] (no
parity) or MBISTDIN[71:0] (parity) | Input | Data to the RAMs. Not all RAMs use the full
width. |
| MBISTADDR[10:0] | Input | Address. Not all RAMs use the full address
width. |
| MBISTBE[23:0] (no
parity) or MBISTBE[71:0] (parity) | Input | MBIST bit enable (no parity) or MBIST byte
enable (parity). |
| MBISTCE[17:0] | Input | Chip enables for each of the RAMs. |
| MBISTWE | Input | Global write enable going to all of the RAMs. |
| MBISTDOUT[255:0] (no parity)
or MBISTDOUT[287:0] (parity) | Output | Data out for all of the RAMs. The RAM is selected
using MBISTCE. |
To enable testing of all CPUs of MPCore in parallel, MBISTDOUT is 256 bits wide. Table C.6 shows the mappings
of the MP11 CPUs to the MBISTDOUT bits.
Note
Some bus widths are different depending on whether parity
checking is implemented or not.
Table C.6. CPU mappings to MBISTOUT bits
| CPU name | CPU data bits | Corresponding MBISTDOUT bits |
|---|
| CPU0 | [63:0] (no parity) or [71:0] (parity) | [63:0] (no parity) or [71:0] (parity) |
| CPU1 | [63:0] (no parity) or [71:0] (parity) | [127:64] (no parity) or [143:72] (parity) |
| CPU2 | [63:0] (no parity) or [71:0] (parity) | [191:128] (no parity) or [215:144] (parity) |
| CPU3 | [63:0] (no parity) or [71:0] (parity) | [255:192] (no parity) or [287:216] (parity) |
Table C.7 shows MBISTCE[17:0] encoding.
Table C.7. MBISTCE encodings
| MBISTCE bit | RAM |
|---|
| MBISTCE[17] | SCU tag RAM way 3 and SCU tag RAM way 2 |
| MBISTCE[16] | SCU tag RAM way 1 and SCU tag RAM way 0 |
| MBISTCE[15] | DData RAM way 3 |
| MBISTCE[14] | DData RAM way 2 |
| MBISTCE[13] | DData RAM way 1 |
| MBISTCE[12] | DData RAM way 0 |
| MBISTCE[11] | DTagRAM way 3 and DTagRAM way 2 |
| MBISTCE[10] | DTagRAM way 1 and DTagRAM way 0 |
| MBISTCE[9] | DDirty RAM |
| MBISTCE[8] | IDataRAM array 7 and IDataRAM array 6 |
| MBISTCE[7] | IDataRAM array 5 and IDataRAM array 4 |
| MBISTCE[6] | IDataRAM array 3 and IDataRAM array 2 |
| MBISTCE[5] | IDataRAM array 1 and IDataRAM array 0 |
| MBISTCE[4] | ITagRAM way 3 and ITagRAM way 2 |
| MBISTCE[3] | ITagRAM way 1 and ITagRAM way 0 |
| MBISTCE[2] | BTAC RAMs |
| MBISTCE[1] | TLB RAM array 1 |
| MBISTCE[0] | TLB RAM array 0 |
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