C.10. Testing MP11 SCU RAM
Table C.23 shows
enabling SCU RAM arrays using MBISTCE[17:16].
Table C.23. Enabling SCU RAM arrays
| Signal | Ways | RAM arrays |
|---|
| MBISTCE[16] | Way 1 and Way 0 | u_tag_ram0, u_tag_ram1, u_tag_ram4, u_tag_ram5, u_tag_ram8, u_tag_ram9, u_tag_ram12,
and u_tag_ram13. |
| MBISTCE[17] | Way 2 and Way 3 | u_tag_ram2, u_tag_ram3, u_tag_ram6, u_tag_ram7, u_tag_ram10, u_tag_ram11, u_tag_ram14,
and u_tag_ram15. |
Figure C.10 shows
the SCU RAM array organization in an MP11 4-CPU configuration from
the MBIST point of view.
Table C.24 shows
the RAM arrays used for each data cache size.
Table C.24. SCU RAM arrays and data cache sizes
| Data cache size | Number of blocks per MP11 CPU | Block size | Address bus |
|---|
| 16KB | 4 | 128x22 (no parity) or 128x25 (parity) | MBISTADDR[6:0] |
| 32KB | 4 | 256x22 (no parity) or 256x25 (parity) | MBISTADDR[7:0] |
| 64KB | 4 | 518x22 (no parity) or 512x25 (parity) | MBISTADDR[8:0] |
Each SCU RAM is 22 bits wide (no parity) or 25 bits wide (with
parity). So, data writes and data reads use the following MBISTDIN and MBISTDOUT mapping for each MP11 CPU shown in Figure C.11.
PDF version