ARM11 MPCore Processor Technical Reference ManualRevision: r2p0
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15.6. ARMv6 Sum of Absolute Differences (SAD)

Table 15.8 shows ARMv6 SAD instructions and gives their cycle timing behavior.

Table 15.8. ARMv6 sum of absolute differences instruction timing behavior

InstructionsCyclesEarly RegResult latency
USAD81<Rm>,<Rs>3[1]
USADA81<Rm>,<Rs>3a

[1] Result latency is one less if the destination is the accumulate for a subsequent USADA8.


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