ARM11 MPCore Processor Technical Reference ManualRevision: r2p0
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9.1.5. SCU Invalidate All Register

The SCU Invalidate All Register invalidates the tag RAMs on a per CPU and per way basis. This operation is atomic, that is, a write transfer to this address only terminates when all the lines have been invalidated. This register reads as 0.

Figure 9.4 shows the format of this register.

Figure 9.4. SCU Invalidate All Register format


Table 9.6 shows the SCU Invalidate All Register bit assignments.

Table 9.6. SCU Invalidate All Register bit assignment

BitsFieldDescription
[31:16]ReservedSBZ.
[15:12]CPU3 ways

Indicates the ways that must be invalidated for MP11 CPU3. Writing to these bits has no effect if the ARM11 MPCore processor has less than four CPUs.

Bit [15] = Way 3

Bit [14] = Way 2

Bit [13] = Way 1

Bit [12] = Way 0.

[11:8]CPU2 ways

Indicates the ways that must be invalidated for MP11 CPU2. Writing to these bits has no effect if the ARM11 MPCore processor has less than three CPUs.

Bit [11] = Way 3

Bit [10] = Way 2

Bit [9] = Way 1

Bit [8] = Way 0.

[7:4]CPU1 ways

Indicates the ways that must be invalidated for MP11 CPU1. Writing to these bits has no effect if the ARM11 MPCore processor has less than two CPUs.

Bit [7] = Way 3

Bit [6] = Way 2

Bit [5] = Way 1

Bit [4] = Way 0.

[3:0]CPU0 ways

Indicates the ways that must be invalidated for MP11 CPU0.

Bit [3] = Way 3

Bit [2] = Way 2

Bit [1] = Way 1

Bit [0] = Way 0.


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