5.6.3. Page table descriptors when using
remapping
Table 5.3 shows
the existing V6 TEX with CB encodings. This can be re-arranged to
provide a mechanism to change the functions of the encodings TEX[0], C
and B provide, using remap registers. TEX[2:1] are then freed up
for software usage. This behavior is only enabled when CP15 register
1, bit [28] is set, so providing backward compatibility with ARMv6.
The result is that if CP15 Register 1, bit [28] is set, the
effect is as shown in Table 5.6.
Table 5.6. New V6 TEX, CB encodings
| Page table encodings | Memory type | Inner cache attributes when
mapped as Normal | Outer cache attributes when
mapped as Normal |
|---|
| TEX | C | B |
|---|
| XX0 | 0 | 0 | PRRR[1:0] | NMRR[1:0] | NMRR[17:16] |
| XX0 | 0 | 1 | PRRR[3:2] | NMRR[3:2] | NMRR[19:18] |
| XX0 | 1 | 0 | PRRR[5:4] | NMRR[5:4] | NMRR[21:20] |
| XX0 | 1 | 1 | PRRR[7:6] | NMRR[7:6] | NMRR[23:22] |
| XX1 | 0 | 0 | PRRR[9:8] | NMRR[9:8] | NMRR[25:24] |
| XX1 | 0 | 1 | PRRR[11:10] | NMRR[11:10] | NMRR[27:26] |
| XX1 | 1 | 0 | RESERVED | RESERVED | RESERVED |
| XX1 | 1 | 1 | PRRR[15:14] | NMRR[15:14] | NMRR[31:30] |
Primary Memory Region Remap Registers (PRRR) and Normal Memory
Region Remap Registers (NMRR) are defined in c10, Memory Region Remap Registers.
Table 5.7. Page attributes and memory types
| Memory type | Shareable attribute when S = 0 | Shareable attribute when S = 1 |
|---|
| Strongly Ordered | Shareable | Shareable |
| Device | PRRR[16] | PRRR[17] |
| Normal | PRRR[18] | PRRR[19] |
To provide different encodings of the Outer cache attributes
from the Inner cache attributes, the MMU remap register permits
the cachable attributes to be remapped to different values.It is
Unpredictable whether the TLB caches the effect of the TEX Remap
on page tables. As a result, the TLB must be invalidated between
changing the TEX Remap bit and relying on the effect of those changes
taking place.
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