3.4.21. c9, Data Cache Lockdown Register

The Data Cache Lockdown Register provides a means to lock down the cache and therefore provide some control over pollution that applications might cause. With these registers you can lock down each cache way independently.

The Data Cache Lockdown Register is:

You can access the Data Cache Lockdown Register by reading or writing CP15 c9 with the CRm field set to c0 and the Opcode_2 field set to 0. For example:

MRC p15, 0, <Rd>, c9, c0, 0 ; Read Data Cache Lockdown Register
MCR p15, 0, <Rd>, c9, c0, 0 ; Write Data Cache Lockdown Register

MP11 CPUs only support one method of using cache lockdown registers, called Format C. This method is a cache way based locking scheme. It enables you to lockdown each cache way independently. This gives you some control over cache pollution caused by particular applications, and provides a traditional lockdown function for locking critical regions into the cache.

A locking bit for each cache way determines if the cache allocation mechanism is able to access that cache way.

MP11 CPUs have an associativity of 4. If all ways are locked, the MP11 CPUs behave as if only ways 3 to 1 are locked and way 0 is unlocked.

Figure 3.35 shows the format of the Data Cache Lockdown Register.

Figure 3.35. Data Cache Lockdown Register format


The L bits for cache ways 3 to 0 are bits [3:0] respectively.

L = 0

Allocation to the cache way is determined by the standard replacement algorithm (reset state).

L = 1

No allocation is performed to this cache way.

A cache lockdown register must only be changed when it is certain that all outstanding accesses that might cause a cache line fill have completed. For this reason, a Data Synchronization Barrier instruction must be executed before the cache lockdown register is changed.

The following procedure for lock down into a data cache way i, with N cache ways, using Format C, ensures that only the target cache way i is locked down.

This is the architecturally defined method for locking data into caches:

  1. Ensure that no processor exceptions can occur during the execution of this procedure, by disabling interrupts. If this is not possible, all code and data that any exception handlers use that can be called must be treated as code and data before step 2.

  2. Ensure that all data used by the following code, apart from the data that is to be locked down, is either:

    • in an uncachable area of memory

    • in an already locked cache way.

  3. Ensure that the data to be locked down is in a Cachable area of memory.

  4. Ensure that the data to be locked down is not already in the cache, using cache Clean and/or Invalidate instructions as appropriate.

  5. Enable allocation to the target cache way by writing to CP15 c9, with the CRm field set to 0, setting L equal to 0 for bit i and L equal to 1 for all other ways.

  6. Ensure that the memory cache line is loaded into the cache by using an LDR instruction to load a word from the memory cache line, for each of the cache lines to be locked down in cache way i.

  7. Write to CP15 c9, CRm = c0, setting L to 1 for bit i and restore all the other bits to the values they had before this routine was started.

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