ARM11 MPCore Processor Technical Reference ManualRevision: r2p0
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3.4.8. c1, Auxiliary Control Register

The Auxiliary Control Register controls:

The Auxiliary Control Register is:

You can use the Auxiliary Control Register to enable and disable program flow prediction operations. It is selected by reading or writing CP15 c1 with the Opcode_2 field set to 1:

MRC p15,0,<Rd>,c1,c0,1; Read Auxiliary Control Register

MCR p15,0,<Rd>,c1,c0,1; Write Auxiliary Control Register

Figure 3.19 shows the format of the Auxiliary Control Register.

Figure 3.19. Auxiliary Control Register format


Table 3.21 shows the bit assignment of the Auxiliary Control Register.

Table 3.21. Auxiliary Control Register bit functions

BitsFieldFunction
[31:7]-

Reserved. These bits must be updated using a read-modify-write technique to ensure that currently unallocated bits are not unnecessarily modified.

[6]L1 parity checking

L1 parity checking enable bit:

0 = disabled, no parity errors are reported

1 = enabled, parity errors are reported through corresponding parity error output signals.

Note

Before enabling L1 parity checking, all caches must be invalidated. The parity checking enable bit can then be set or cleared without restriction. Parity information in the RAMs is always generated and kept up-to-date. Only error reporting is masked by this bit.

[5]SMP/nAMP mode

Signals if the CPU is taking part in coherency or not:

0 = AMP mode, the CPU is not taking part in coherency

1 = SMP mode, the CPU is taking part in coherency.

See AMP mode and SMP mode.

[4]EXCL

This bit enables the exclusive behavior of L1 if the processor is used in conjunction with an L2 cache supporting that behavior:

0 = L1 and L2 caches are inclusive (default)

1 = L1 and L2 caches are exclusive.

[3]FInstruction folding enable. This bit enables the use of instruction folding if program flow prediction is enabled. See c1, Control Register.
[2]SB

Static branch prediction enable. This bit enables the use of static branch prediction if program flow prediction is enabled. See c1, Control Register.

0 = static branch prediction is disabled

1 = static branch prediction is enabled.

This bit is set on reset.

[1]DB

Dynamic branch prediction enable. This bit enables the use of dynamic branch prediction if program flow prediction is enabled. See c1, Control Register.

0 = dynamic branch prediction is disabled

1 = dynamic branch prediction is enabled.

This bit is set on reset.

[0]RS

Return stack enable. This bit enables the use of the return stack if program flow prediction is enabled. See c1, Control Register.

0 = return stack is disabled

1 = return stack is enabled.

This bit is set on reset.


AMP mode and SMP mode

By default, the processor is in AMP mode (bit [5] reset to 0). To prevent coherent data corruption, the sequence to enable SMP mode for MP11 CPUs is:

  1. If the SCU is disabled, enable it by writing a 1 to the SCU enable bit of the SCU Control Register.

    Note

    ARM recommends that you invalidate the SCU tag RAMs before enabling the SCU. Invalidate the SCU tag RAMs with the appropriate command in the SCU Invalidate All Register. Not invalidating the SCU tag RAMs incurs a performance penalty.

  2. Write the SMP/nAMP bit as 1.

  3. Disable interrupts.

  4. Clean and invalidate the data cache.

  5. Enable interrupts.

Similarly, the sequence to enable AMP mode for MP11 CPUs is:

  1. Disable interrupts.

  2. Clean and invalidate the data cache.

  3. Write the SMP/nAMP bit as 0.

  4. Data Synchronization Barrier.

  5. Enable interrupts.

Note

In AMP mode, shared write-back write-allocate regions are treated as noncacheable like other shared regions.

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