ARM11 MPCore Processor Technical Reference Manual: 5.10. Fault status and address

5.10. Fault status and address

Table 5.11 shows the encodings for the Fault Status Register.

Table 5.11. Fault Status Register encoding

Priority	Sources		FSR[10,3:0]	Domain	FAR	SLVER/ DECERR	R/W
Highest	Alignment		b00001	Invalid	Valid	Invalid	Valid
	Instruction cache maintenance^[1] operation fault		b00100	Invalid	Valid	Invalid	Invalid
	External Abort on translation	First-level	b01100	Invalid	Valid	Valid	Valid
	External Abort on translation	Second-level	b01110	Valid	Valid	Valid	Valid
	Translation	Section	b00101	Invalid	Valid	Invalid	Valid
		Page	b00111	Valid	Valid	Invalid	Valid
	Access bit	Section	b00011	Invalid	Valid	Invalid	Valid
	Access bit	Page	b00110	Valid	Valid	Invalid	Valid
	Domain	Section	b01001	Valid	Valid	Invalid	Valid
		Page	b01011	Valid	Valid	Invalid	Valid
	Permission	Section	b01101	Valid	Valid	Invalid	Valid
		Page	b01111	Valid	Valid	Invalid	Valid
	Precise External Abort	-	b01000	Valid	Valid	Invalid	Valid
	Imprecise External Abort		b10110	Invalid	Invalid	Valid	Valid
Lowest	Debug event		b00010	Valid	Invalid	Invalid	Invalid
^[1]These aborts cannot be signaled with the IFSR because they do not occur on the instruction side.

Note

All other Fault Status Register encodings are reserved.

If a translation abort occurs during a data cache maintenance operation by Virtual Address, then a Data Abort is taken and the DFSR indicates the reason. The FAR indicates the faulting address.

If a translation abort occurs during an Instruction cache maintenance operation by Virtual Address, then a Data Abort is taken, and an Instruction cache maintenance operation fault is indicated in the DFSR. The FAR indicates the faulting address.

Domain and fault address information is only available for data accesses. For instruction aborts r14 must be used to determine the faulting address. You can determine the domain information by performing a TLB lookup for the faulting address and extracting the domain field.

Table 5.12 is a summary of which abort vector is taken, and which of the Fault Status and Fault Address Registers are updated for each abort type.

Table 5.12. Summary of aborts

Abort type	Abort taken	Precise?	Register updated?
Abort type	Abort taken	Precise?	IFSR	WFAR	DFSR	FAR
Instruction MMU fault	Prefetch Abort	Yes	Yes	No	No	No
Instruction Debug Abort	Prefetch Abort	Yes	Yes	No	No	No
Instruction External Abort on translation	Prefetch Abort	Yes	Yes	No	No	No
Instruction External Abort	Prefetch Abort	Yes	Yes	No	No	No
Memory barrier maintenance operation	Data Abort	Yes	Yes	Yes^[1]	Yes	Yes
Data MMU fault	Data Abort	Yes	No	Yes^a	Yes	Yes
Data Debug Abort	Data Abort	No	No	Yes	Yes	Yes^[2]
Data External Abort on translation	Data Abort	Yes	No	Yes^a	Yes	Yes
Data External Abort	Data Abort	No^[3]	No	No	Yes	No
Data cache maintenance operation	Data Abort	Yes	No	Yes^a	Yes	Yes
^[1]Although the WFAR is updated by the processor the behavior is architecturally Unpredictable. ^[2]The processor updates the FAR with an Unpredictable value. ^[3]Data Aborts can be precise, see External aborts for more details.

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