Most of the MP11 CPU control operations are through CP15 instructions. These operations are not applicable to ARM11 MPCore processor global control. ARM11 MPCore processor global control and peripherals must be accessed through memory-mapped transfers. To reduce the complexity of the system and hide these transactions from the L2 memory system, all registers accessible by all MP11 CPUs within MPCore are grouped into two contiguous 4KB pages accessed through a dedicated internal bus. These pages are relocatable through a base address defined using pins PERIPHBASE[18:0]. Value assigned to PERIPHBASE[18:0] does not correspond to the 19 most significant bit of the memory map base address for the ARM11 MPcore private memory region.

Any transaction to addresses of the form {PERIPHBASE[18:0], 13’address_low_bits} is redirected to the MPCore private memory region.

Table 9.1 shows register addresses for the ARM11 MPCore processor relative to this base address.