ARM11 MPCore Processor Technical Reference Manual: 15.11. Load and store double instructions

15.11. Load and store double instructions

This section describes the cycle timing behavior for the LDRD and STRD instructions

The LDRD and STRD instructions:

Are 2-cycle issue if either a negative register offset or a shift other than LSL #2 is used. Only the offset register is an Early Reg.
Are single-cycle issue if either a constant offset is used or if a register offset with no shift, or shift by 2 is used. Both the base and any offset register are Early Regs.
Take only one memory cycle if the address is doubleword aligned.
Take two memory cycles if the address is not doubleword aligned.

The updated base register has a result latency of one. For back-to-back load/store instructions with base write back, the updated base is available to the following load/store instruction with a result latency of 0.

To prevent instructions after a STRD from writing to a register before it has stored that register, the STRD registers have a lock latency that determines how many cycles it is before a subsequent instruction which writes to that register can start.

Table 15.16 shows the cycle timing behavior for LDRD and STRD instructions.

Table 15.16. Load and store double instructions cycle timing behavior

Example instruction		Cycles	Memory cycles	Result latency (LDRD)	Register lock latency (STRD)
Address is double-word aligned
	`LDRD r1, <addr_md_1cycle>`^[1]	1	1	3/3	1,2
	`LDRD r1, <addr_md_2cycle>`^a	2	2	4/4	2,3
Address not double-word aligned
	`LDRD r1, <addr_md_1cycle>`^a	1	2	3/4	1,2
	`LDRD r1, <addr_md_2cycle>`^a	2	3	4/5	2,3
^[1]See Table 15.17 for an explanation of `<addr_md_1cycle>` and `<addr_md_2cycle>`.

Table 15.17 shows the explanation of <addr_md_1cycle> and <addr_md_2cycle> used in Table 15.16.

Table 15.17. <addr_md_1cycle> and <addr_md_2cycle> LDRD example instruction

Example instruction		Early Reg	Comment
`<addr_md_1cycle>`
	`LDRD <Rd>, [<Rn>, #cns] (!)`	<Rn>	If an immediate offset, or a positive register offset with no shift or shift LSL #2, then one-issue cycle.
	`LDRD <Rd>, [<Rn>, <Rm>] (!)`	<Rn>, <Rm>
	`LDRD <Rd>, [<Rn>, <Rm>, LSL #2] (!)`	<Rn>, <Rm>
	`LDRD <Rd>, [<Rn>], #cns`	<Rn>
	`LDRD <Rd>, [<Rn>], <Rm>`	<Rn>, <Rm>
	`LDRD <Rd>, [<Rn>], <Rm>, LSL #2`	<Rn>, <Rm>
`<addr_md_2cycle>`
	`LDRD <Rd>, [<Rn>, -<Rm>] (!)`	<Rm>	If negative register offset, or shift other than LSL #2 then two-issue cycles.
	`LDRD Rd, [<Rm>, -<Rm> <shf> <cns>] (!)`	<Rm>
	`LDRD <Rd>, [<Rn>], -<Rm>`	<Rm>
	`LDRD< Rd>, [Rn], -<Rm> <shf> <cns>`	<Rm>

Copyright © 2005, 2006, 2008. All rights reserved.	ARM DDI 0360F
Non-Confidential
PDF version