ARM11 MPCore Processor Technical Reference ManualRevision: r2p0
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15.5. ARMv6 media data processing

Table 15.7 shows ARMv6 media data processing instructions and gives their cycle timing behavior.

All ARMv6 media data processing instructions are single-cycle issue instructions. These instructions produce their results in either the ALU or Sat stage, and have result latencies of one or two accordingly. Some of the instructions require an input register to be shifted before use and therefore are marked as requiring an Early Reg.

Table 15.7. ARMv6 media data processing instructions cycle timing behavior

InstructionsCyclesEarly RegResult latency
SADD16, SSUB16, SADD8, SSUB81-1
USAD8, USADA81<Rm>,<Rs>3
UADD16, USUB16, UADD8, USUB81-1
SEL1-1
QADD16, QSUB16, QADD8, QSUB81-2
SHADD16, SHSUB16, SHADD8, SHSUB81-2
UQADD16, UQSUB16, UQADD8, UQSUB81-2
UHADD16, UHSUB16, UHADD8, UHSUB81-2
SSAT16, USAT161-2
SADDSUBX, SSUBADDX1<Rm>1
UADDSUBX, USUBADDX1<Rm>1
SADD8TO16, SADD8TO32, SADD16TO321<Rm>1
SUNPK8TO16, SUNPK8TO32, SUNPK16TO321<Rm>1
UUNPK8TO16, UUNPK8TO32, UUNPK16TO321<Rm>1
UADD8TO16, UADD8TO32, UADD16TO321<Rm>1
REV, REV16, REVSH1<Rm>1
PKHBT, PKHTB1<Rm>1
SSAT, USAT1<Rm>2
QADDSUBX, QSUBADDX1<Rm>2
SHADDSUBX, SHSUBADDX1<Rm>2
UQADDSUBX, UQSUBADDX1<Rm>2
UHADDSUBX, UHSUBADDX1<Rm>2

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