ARM11 MPCore Processor Technical Reference ManualRevision: r2p0
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9.1.1. SCU-specific registers

Table 9.2 shows the SCU-specific registers. Addresses are given relative to the base address of the region for the SCU in the private memory region memory map. All SCU registers are byte accessible.

Table 9.2. SCU register definition

OffsetNameReset valueTypeDescription
0x00Control Register0x00001FFER/W See SCU Control Register.
0x04Configuration RegisterImplementation DefinedROSee SCU Configuration Register
0x08SCU CPU Status-R/WSee SCU CPU Status Register.
0x0CInvalidate all-WOSee SCU Invalidate All Register.
0x10Performance Monitor Control Register0x00000000R/WSee Performance Monitor Control Register.
0x14Monitor Counter Events 00x00000000R/WSee Performance monitor event registers
0x18Monitor Counter Events 10x00000000R/W
0x1CMonitor Counter 00x00000000R/W See Count registers, MN0-MN7
0x20Monitor Counter 10x00000000R/W
0x24Monitor Counter 20x00000000R/W
0x28Monitor Counter 30x00000000R/W
0x2CMonitor Counter 40x00000000R/W
0x30Monitor Counter 50x00000000R/W
0x34Monitor Counter 60x00000000R/W
0x38Monitor Counter 70x00000000R/W
0x3C - 0xFCReserved--RAZ

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