ARM11 MPCore Processor Technical Reference Manual: 3.4.20. c8, TLB Operations Register

3.4.20. c8, TLB Operations Register

The TLB Operations Register either:

invalidates all the unlocked entries in the TLB
invalidates all TLB entries for an area of memory before the MMU remaps it
invalidates all TLB entries that match an ASID value.

The TLB Operations Register is:

in CP15 c8
a 32-bit write-only register
accessible in privileged modes only.

The TLB Operations Register, CP15 c8, is a write-only register used to manage the Translation Lookaside Buffer (TLB).

The defined TLB operations are listed in Table 3.33. The function to be performed is selected by the Opcode_2 and CRm fields in the MCR instruction used to write CP15 c8. Writing other Opcode_2 or CRm values is Unpredictable.

Reading from CP15 c8 is Unpredictable.

Table 3.33 shows the TLB Operations Register instructions.

Table 3.33. TLB Operations Register instructions

Function	Data	Instruction
Invalidate TLB	SBZ	`MCR p15,0,<Rd>,c8,<CRm>,0`
Invalidate TLB Single Entry by MVA with ASID match	MVA/ASID	`MCR p15,0,<Rd>,c8,<CRm>,1`
Invalidate TLB Entries on ASID Match	ASID	`MCR p15,0,<Rd>,c8,<CRm>,2`
Invalidate TLB Single Entry on MVA only	MVA	`MCR p15,0,<Rd>,c8,<CRm>,3`

The CRm value indicates to the hardware what type of access caused the TLB function to be invoked.

Table 3.34 shows the CRm values for the TLB Operations Register, and their meanings. All other CRm values are reserved

Table 3.34. CRm values for TLB Operations Register

CRm	Meaning
c5	Instruction TLB operation
c6	Data TLB operation
c7	Unified TLB operation

Note

The processor has a unified TLB. Any TLB operations specified for Instruction or Data TLB perform the equivalent operation on the unified TLB.

The Invalidate TLB Single Entry operation uses the Virtual Address as an argument. Figure 3.33 shows the Virtual Address format of the TLB Operations Register.

Figure 3.33. TLB Operations Register Virtual Address format

The Invalidate TLB Entries on ASID Match operation requires an ASID as an argument. Figure 3.34 shows the ASID format of the TLB Operations Register.

Figure 3.34. TLB Operations Register ASID format

Functions that update the contents of the TLB occur in program order. Therefore, an explicit data access before the TLB function uses the old TLB contents, and an explicit data access after the TLB function uses the new TLB contents. For instruction accesses, TLB updates are guaranteed to have taken effect before the next pipeline flush. This includes flush prefetch buffer operations and exception return sequences.

Invalidate TLB

Invalidate TLB invalidates all the unlocked entries in the TLB.

Invalidate TLB Single Entry

You can use Invalidate TLB Single Entry to invalidate an area of memory before remap. You must perform an Invalidate TLB Single Entry of a Virtual Address (VA) in each area to be remapped (section, small page, or large page).

This function invalidates a TLB entry that matches the provided VA and ASID, or a global TLB entry that matches the provided VA. This function invalidates a matching locked entry.

Invalidate TLB Entries on ASID Match

This is a single interruptible operation that invalidates all TLB entries that match the provided ASID value. This function invalidates locked entries. Entries marked as global are not invalidated by this function.

In MP11 CPUs, this operation takes several cycles to complete and the instruction is interruptible. When interrupted the r14 state is set to indicate that the MCR instruction has not executed. Therefore, r14 points to the address of the MCR + 4. The interrupt routine then automatically restarts at the MCR instruction.If this operation is interrupted and later restarted, any entries fetched into the TLB by the interrupt that uses the provided ASID are invalidated by the restarted invalidation.

Invalidate TLB entries on MVA only

You can use Invalidate TLB Entries to invalidate an area of memory prior to remapping. You must perform an Invalidate TLB Single Entry of a Virtual Address (VA) in each area to be remapped (section, small page, or large page).

This function invalidates a TLB entry that matches the provided VA. This entry can be global or nonglobal. If the entry is nonglobal the ASID matching is ignored. This function invalidates a matching locked entry.

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