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Complex instruction dependencies and memory system interactions make it impossible to describe briefly the exact cycle timing behavior for all instructions in all circumstances. The timings described in this chapter are accurate in most cases. If precise timings are required you must use a cycle-accurate model of the MP11 CPUs.
Unless stated otherwise cycle counts and result latencies described in this chapter are best case numbers. They assume:
no outstanding data dependencies between the current instruction and a previous instruction
the instruction does not encounter any resource conflicts
all data accesses hit in the MicroTLB and data cache, and do not cross protection region boundaries
all instruction accesses hit in the instruction cache.
This section describes:
| Copyright © 2005, 2006, 2008. All rights reserved. | ARM DDI 0360F |
| Non-Confidential | |
| PDF version | |
| Home > Cycle Timings and Interlock Behavior > About cycle timings and interlock behavior |