14.1.4. Pipeline advance interface

There are three points in the MPCore pipeline at which signals are produced for the ETM. These signals must be realigned by the ETM, so pipeline advance signals are provided.

The pipeline advance signals indicate when a new instruction enters pipeline stages Ex3, Ex2, and ADD, see Typical pipeline operations.

Table 14.7 shows the ETMPADV[2:0] pipeline advance interface signals.

Table 14.7. ETMPADV[2:0]

BitsReference nameDescriptionQualified by
[2]

PAEx3[1]

Instruction entered Ex3-
[1]

PAEx2[1]

Instruction entered Ex2-
[0]

PAAdd[1]

Instruction entered Ex1 and ADD-

[1] This is kept LOW when the ETM is powered down.


The pipeline advance signals present in other interfaces are:

IAValid

Instruction entered WBEx.

DASlot != 00

Data transfer entered DC1.

DDSlot != 00, DDRWSlot != 0, or DDWSlot != 00

Data transfer entered WBls.

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