ARM11 MPCore™ Processor Technical Reference Manual

Revision: r2p0


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Conventions
Further reading
Feedback
Feedback on this product
Feedback on this book
1. Introduction
1.1. About the processor
1.2. Extensions to ARMv6
1.3. MP11 CPU overview
1.3.1. Integer core
1.3.2. Load Store Unit (LSU)
1.3.3. Prefetch unit
1.3.4. Memory system
1.4. Debug and programming support
1.4.1. Debug
1.4.2. Vector Floating-Point (VFP)
1.4.3. System control
1.4.4. Interrupt handling
1.5. Power management
1.6. Configurable options
1.7. Pipeline stages
1.8. Typical pipeline operations
1.8.1. Instruction progression
1.9. MPCore architecture with Jazelle technology
1.9.1. Instruction compression
1.9.2. The Thumb instruction set
1.9.3. Java bytecodes
1.10. Parity checking support
1.11. Product revisions
2. Programmers Model
2.1. About the programmers model
2.2. Processor operating states
2.2.1. Switching state
2.2.2. Interworking ARM and Thumb state
2.3. Instruction length
2.4. Data types
2.5. Memory formats
2.5.1. 32-bit byte-invariant BE-8 format
2.5.2. Little-endian format
2.6. Addresses in an MPCore system
2.7. Operating modes
2.8. Registers
2.8.1. The ARM state register set
2.8.2. The Thumb state register set
2.8.3. Accessing high registers in Thumb state
2.8.4. ARM state and Thumb state registers relationship
2.9. The program status registers
2.9.1. The condition code flags
2.9.2. The Q flag
2.9.3. The J bit
2.9.4. The GE[3:0] bits
2.9.5. The E bit
2.9.6. The A bit
2.9.7. The control bits
2.9.8. Modification of PSR bits by MSR instructions
2.9.9. Reserved bits
2.10. Exceptions
2.10.1. New instructions for exception handling
2.10.2. Exception entry and exit summary
2.10.3. Entering an ARM exception
2.10.4. Leaving an ARM exception
2.10.5. Reset
2.10.6. Fast interrupt request
2.10.7. Interrupt request
2.10.8. Aborts
2.10.9. Imprecise Data Abort mask in the CPSR/SPSR
2.10.10. Software interrupt instruction
2.10.11. Undefined instruction
2.10.12. Breakpoint instruction
2.10.13. Exception vectors
2.10.14. Exception priorities
3. Control Coprocessor CP15
3.1. About control coprocessor CP15
3.1.1. Accessing CP15 registers
3.2. CP15 registers arranged by function
3.3. Summary of control coprocessor CP15 registers and operations
3.4. Register descriptions
3.4.1. c0, Main ID Register
3.4.2. c0, Cache Type Register
3.4.3. c0, TLB Type Register
3.4.4. c0, CPU ID Register
3.4.5. c0, Feature registers
3.4.6. c0, Instruction Set Attributes Registers
3.4.7. c1, Control Register
3.4.8. c1, Auxiliary Control Register
3.4.9. c1, Coprocessor Access Control Register
3.4.10. c2, Translation Table Base Register 0
3.4.11. c2, Translation Table Base Register 1
3.4.12. c2, Translation Table Base Control Register
3.4.13. c3, Domain Access Control Register
3.4.14. c5, Data Fault Status Register
3.4.15. c5, Instruction Fault Status Register
3.4.16. c6, Fault Address Register
3.4.17. c6, Watchpoint Fault Address Register
3.4.18. c7, Cache Operations Register
3.4.19. c7, VA to PA operations
3.4.20. c8, TLB Operations Register
3.4.21. c9, Data Cache Lockdown Register
3.4.22. c10, TLB Lockdown Register
3.4.23. c10, Memory Region Remap Registers
3.4.24. c13, FCSE PID Register
3.4.25. c13, Context ID Register
3.4.26. c13, Thread ID registers
3.4.27. c15, Performance Monitor Control Register (PMNC)
3.4.28. c15, Cycle Counter Register (CCNT)
3.4.29. c15, Count Register 0 (PMN0) and Count Register 1 (PMN1)
3.4.30. c15, TLB Debug Control Register
3.4.31. c15, TLB lockdown operations
3.5. Summary of CP15 instructions
4. Unaligned and Mixed-Endian Data Access Support
4.1. About unaligned and mixed-endian support
4.2. Unaligned access support
4.2.1. Word-invariant mode support
4.2.2. ARMv6 extensions
4.2.3. Word-invariant mode and ARMv6 configurations
4.2.4. Word-invariant data access in ARMv6 (U=0)
4.2.5. Support for unaligned data access in ARMv6 (U=1)
4.2.6. ARMv6 unaligned data access restrictions
4.3. Unaligned data access specification
4.3.1. Load unsigned byte, endian independent
4.3.2. Load signed byte, endian independent
4.3.3. Store byte, endian independent
4.3.4. Load unsigned halfword, little-endian
4.3.5. Load unsigned halfword, big-endian
4.3.6. Load signed halfword, little-endian
4.3.7. Load signed halfword, big-endian
4.3.8. Store halfword, little-endian
4.3.9. Store halfword, big-endian
4.3.10. Load word, little-endian
4.3.11. Load word, big-endian
4.3.12. Store word, little-endian
4.3.13. Store word, big-endian
4.3.14. Load double, load multiple, load coprocessor (little-endian, E = 0)
4.3.15. Load double, load multiple, load coprocessor (big-endian, E=1)
4.3.16. Store double, store multiple, store coprocessor (little-endian, E=0)
4.3.17. Store double, store multiple, store coprocessor (big-endian, E=1)
4.4. Operation of unaligned accesses
4.5. Mixed-endian access support
4.5.1. ARMv6 support for mixed-endian data
4.5.2. Reset values of the EE, U, and E bits
4.6. Instructions to reverse bytes in a general-purpose register
4.6.1. All load and store operations
4.7. Instructions to change the CPSR E bit
5. Memory Management Unit
5.1. About the MMU
5.2. TLB organization
5.2.1. MicroTLB
5.2.2. Main TLB
5.2.3. TLB control operations
5.2.4. Page-based attributes
5.2.5. Coherency
5.2.6. Supersections
5.3. Memory access sequence
5.3.1. TLB match process
5.4. Enabling and disabling the MMU
5.4.1. Enabling the MMU
5.4.2. Disabling the MMU
5.5. Memory access control
5.5.1. Domains
5.5.2. Access permissions
5.5.3. Execute never bits
5.5.4. Access permission and ForceAP bit
5.6. Memory region attributes
5.6.1. C and B bit, and type extension field encodings
5.6.2. Shared
5.6.3. Page table descriptors when using remapping
5.7. Memory attributes and types
5.7.1. Normal memory attribute
5.7.2. Device memory attribute
5.7.3. Strongly Ordered memory attribute
5.7.4. Ordering requirements for memory accesses
5.7.5. Explicit memory barriers
5.7.6. Backwards compatibility
5.8. MMU aborts
5.8.1. External aborts
5.9. MMU fault checking
5.9.1. Fault checking sequence
5.9.2. Alignment fault
5.9.3. Translation fault
5.9.4. Access bit fault
5.9.5. Domain fault
5.9.6. Permission fault
5.9.7. Debug event
5.10. Fault status and address
5.11. Hardware page table translation
5.11.1. Backwards-compatible page table translation (subpage AP bits enabled)
5.11.2. ARMv6 page table translation subpage AP bits disabled
5.11.3. Restrictions on page table mappings for the instruction cache
5.12. MMU descriptors
5.12.1. First-level descriptor address
5.12.2. First-level descriptor
5.12.3. Second-level page table walk
5.13. MMU software-accessible registers
5.14. MMU and Write Buffer
6. Program Flow Prediction
6.1. About program flow prediction
6.2. Branch prediction
6.2.1. Enabling program flow prediction
6.2.2. Dynamic branch predictor
6.2.3. Static branch predictor
6.2.4. Branch folding
6.2.5. Incorrect predictions and correction
6.3. Return stack
6.4. Memory Barriers
6.4.1. Instruction Memory Barriers (IMBs)
7. Level 1 Memory System
7.1. Coherency protocol
7.1.1. Optimizations
7.2. About the Level 1 data side memory system
7.2.1. Slots Unit
7.2.2. Noncachable accesses
7.2.3. Locked accesses
7.2.4. External Aborts handling
7.2.5. MicroTLB
7.2.6. Cache arbiter
7.2.7. Store buffer
7.2.8. Linefill buffers
7.2.9. DDI buffer
7.2.10. Eviction buffer
7.3. About the Level 1 instruction side memory system
7.4. TLB organization
7.4.1. MicroTLB
7.4.2. Main TLB
8. Level 2 Memory System
8.1. MPCore Level 2 interface
8.1.1. MPCore Level 2 interface overview
8.1.2. AXI transaction IDs
8.1.3. Using the STRT instruction
8.2. L2 exclusive mode
8.3. Synchronization operations
8.3.1. Exclusive loads and stores
8.4. The ACLKEN signal
9. MPCore Private Memory Region
9.1. About the MPCore private memory region
9.1.1. SCU-specific registers
9.1.2. SCU Control Register
9.1.3. SCU Configuration Register
9.1.4. SCU CPU Status Register
9.1.5. SCU Invalidate All Register
9.1.6. Performance Monitor Control Register
9.1.7. Performance monitor event registers
9.1.8. Count registers, MN0-MN7
9.2. Timer and watchdog blocks
9.2.1. Calculating timer intervals
9.2.2. Timer and watchdog registers
9.2.3. Timer Load Register, 0x00
9.2.4. Timer Counter Register, 0x04
9.2.5. Timer Control Register, 0x08
9.2.6. Timer Interrupt Status Register, 0x0C
9.2.7. Watchdog Load Register, 0x20
9.2.8. Watchdog Counter Register, 0x24
9.2.9. Watchdog Control Register, 0x28
9.2.10. Watchdog Interrupt Status Register, 0x2C
9.2.11. Watchdog Reset Status Register, 0x30
9.2.12. Watchdog Disable Register, 0x34
10. MPCore Distributed Interrupt Controller
10.1. About the Distributed Interrupt Controller
10.1.1. Distributed Interrupt Controller clock frequency
10.2. Terminology
10.3. Interrupt Distributor
10.3.1. Interrupt Distributor overview
10.3.2. Behavior of the Interrupt Distributor
10.4. CPU interrupt interfaces
10.5. Interrupt Distributor Registers
10.5.1. Interrupt Distributor Control Register, 0x000
10.5.2. Interrupt Controller Type Register, 0x004
10.5.3. Interrupt Enable clear and Enable set registers, 0x100-0x11C and 0x180-0x19C
10.5.4. Interrupt Pending clear and Pending set registers, 0x200-0x21C and 0x280-0x29C
10.5.5. Active Bit Registers, 0x300-0x31C
10.5.6. Interrupt Priority Registers, 0x400-0x4FC
10.5.7. Interrupt CPU Targets Registers, 0x800-0x8FC
10.5.8. Interrupt Configuration Registers, 0xC00-0xC3C
10.5.9. Interrupt Line Level Registers, 0xD00-0xD1C
10.5.10. Software Interrupt Register, 0xF00
10.6. CPU Interrupt Interface Registers
10.6.1. CPU Interface Control Register, 0x00
10.6.2. Priority Mask Register, 0x04
10.6.3. Binary Point Register, 0x08
10.6.4. Interrupt Acknowledge Register, 0x0C
10.6.5. End of Interrupt (EOI) Register, 0x10
10.6.6. Running Priority Register, 0x14
10.6.7. Highest Pending Interrupt Register, 0x18
11. Clocking, Resets, and Power Management
11.1. Clocking
11.1.1. Synchronous clocking
11.2. Reset
11.3. Reset modes
11.3.1. Power-on reset
11.3.2. Individual power-on reset
11.3.3. Soft reset
11.3.4. DBGTAP reset
11.3.5. Normal operation
11.4. About power consumption control
11.5. Individual MP11 CPU power control
11.5.1. Run mode
11.5.2. Wait For Interrupt (WFI/WFE) mode
11.5.3. Dormant mode
11.5.4. Shutdown mode
11.5.5. Communication to the Power Management Controller
11.6. IEM support
11.6.1. MPCore voltage domains
11.7. Debug
12. Debug
12.1. Debug systems
12.1.1. The debug host
12.1.2. The protocol converter
12.1.3. The MP11 CPU
12.2. About the debug unit
12.2.1. Halting debug-mode debugging
12.2.2. Monitor debug-mode debugging
12.2.3. Virtual Addresses and debug
12.2.4. Programming the debug unit
12.3. Debug registers
12.3.1. Accessing debug registers
12.3.2. CP14 c0, Debug ID Register (DIDR)
12.3.3. CP14 c1, Debug Status and Control Register (DSCR)
12.3.4. CP14 c5, Data Transfer Registers (DTR)
12.3.5. CP14 c7, Vector Catch Register (VCR)
12.3.6. CP14 c64-c69, Breakpoint Value Registers (BVR)
12.3.7. CP14 c80-c85, Breakpoint Control Registers (BCR)
12.3.8. CP14 c96-c97, Watchpoint Value Registers (WVR)
12.3.9. CP14 c112-c113, Watchpoint Control Registers (WCR)
12.4. CP14 registers reset
12.5. CP14 debug instructions
12.5.1. Executing CP14 debug instructions
12.6. Debug events
12.6.1. Software debug event
12.6.2. External debug request signal
12.6.3. Halt DBGTAP instruction
12.6.4. Behavior of the processor on debug events
12.6.5. Effect of a debug event on CP15 registers
12.7. Debug exception
12.8. Debug state
12.8.1. Behavior of the PC in debug state
12.8.2. Interrupts
12.8.3. Exceptions
12.9. Debug communications channel
12.10. Debugging in a system with TLBs
12.11. Monitor debug-mode debugging
12.11.1. Entering the monitor target
12.11.2. Setting breakpoints, watchpoints, and vector catch debug events
12.11.3. Setting software breakpoint debug events (BKPT)
12.11.4. Using the debug communications channel
12.12. Halting debug-mode debugging
12.12.1. Entering debug state
12.12.2. Exiting debug state
12.12.3. Programming debug events
12.13. External signals
13. Debug Test Access Port
13.1. Debug Test Access Port and Halting debug-mode
13.2. Synchronizing RealView ICE
13.3. Entering debug state
13.4. Exiting debug state
13.5. DBGTAP controller overview
13.6. Debug registers
13.6.1. Bypass register
13.6.2. Device ID code register
13.6.3. Instruction Register
13.6.4. Scan chain select register (SCREG)
13.6.5. Scan chains
13.6.6. Reset
13.7. Using the Debug Test Access Port
13.7.1. Entering and leaving debug state
13.7.2. Executing instructions in debug state
13.7.3. Using the ITRsel IR instruction
13.7.4. Transferring data between the host and the core
13.7.5. Using the debug communications channel
13.7.6. Target to host debug communications channel sequence
13.7.7. Host to target debug communications channel
13.7.8. Transferring data in debug state
13.7.9. Example sequences
13.8. Debug sequences
13.8.1. Debug macros
13.8.2. General setup
13.8.3. Forcing the processor to halt
13.8.4. Entering debug state
13.8.5. Leaving debug state
13.8.6. Reading a current mode ARM register in the range r0-r14
13.8.7. Writing a current mode ARM register in the range r0-r14
13.8.8. Reading the CPSR/SPSR
13.8.9. Writing the CPSR/SPSR
13.8.10. Reading the PC
13.8.11. Writing the PC
13.8.12. General notes about reading and writing memory
13.8.13. Reading memory as words
13.8.14. Writing memory as words
13.8.15. Reading memory as halfwords or bytes
13.8.16. Writing memory as halfwords/bytes
13.8.17. Coprocessor register reads and writes
13.8.18. Reading coprocessor registers
13.8.19. Writing coprocessor registers
13.9. Programming debug events
13.9.1. Reading registers using scan chain 7
13.9.2. Writing registers using scan chain 7
13.9.3. Setting breakpoints, watchpoints and vector catches
13.9.4. Setting software breakpoints
13.10. Monitor debug-mode debugging
13.10.1. Receiving data from the core
13.10.2. Sending data to the core
14. Trace Interface Port
14.1. About the ETM interface
14.1.1. Instruction interface
14.1.2. Data address interface
14.1.3. Data value interface
14.1.4. Pipeline advance interface
14.1.5. Coprocessor interface
14.1.6. Other connections to the core
15. Cycle Timings and Interlock Behavior
15.1. About cycle timings and interlock behavior
15.1.1. Changes in instruction flow overview
15.1.2. Definition of terms
15.1.3. Instruction execution overview
15.1.4. Conditional instructions
15.1.5. Opposite condition code checks
15.2. Register interlock examples
15.3. Data processing instructions
15.3.1. Cycle counts if destination is not the PC
15.3.2. Cycle counts if destination is the PC
15.3.3. Example interlocks
15.4. QADD, QDADD, QSUB, and QDSUB instructions
15.5. ARMv6 media data processing
15.6. ARMv6 Sum of Absolute Differences (SAD)
15.6.1. Example interlocks
15.7. Multiplies
15.8. Branches
15.9. Processor state updating instructions
15.10. Single load and store instructions
15.10.1. Base register update
15.11. Load and store double instructions
15.12. Load and store multiple instructions
15.12.1. Load and store multiples, other than load multiples including the PC
15.12.2. Load multiples, where the PC is in the register list
15.12.3. Example interlocks
15.13. RFE and SRS instructions
15.14. Synchronization instructions
15.15. Coprocessor instructions
15.16. SWI, BKPT, Undefined, and Prefetch Aborted instructions
15.17. Thumb instructions
16. Introduction to VFP
16.1. About the VFP11 coprocessor
16.2. Applications
16.3. Coprocessor interface
16.4. VFP11 coprocessor pipelines
16.4.1. FMAC pipeline
16.4.2. DS pipeline
16.4.3. LS pipeline
16.5. Modes of operation
16.5.1. Full-compliance mode
16.5.2. Flush-to-zero mode
16.5.3. Default NaN mode
16.5.4. RunFast mode
16.6. Short vector instructions
16.7. Parallel execution of instructions
16.8. VFP11 treatment of branch instructions
16.9. Writing optimal VFP11 code
16.10. VFP11 revision information
17. VFP Register File
17.1. About the register file
17.2. Register file internal formats
17.2.1. Integer data format
17.2.2. Single-precision data format
17.2.3. Double-precision data format
17.3. Decoding the register file
17.4. Loading operands from ARM11 registers
17.5. Maintaining consistency in register precision
17.6. Data transfer between memory and VFP11 registers
17.7. Access to register banks in CDP operations
17.7.1. About register banks
17.7.2. Operations using register banks
18. VFP Programmers Model
18.1. About the programmers model
18.2. Compliance with the IEEE 754 standard
18.2.1. An IEEE 754 standard-compliant implementation
18.2.2. Complete implementation of the IEEE 754 standard
18.2.3. IEEE 754 standard implementation choices
18.3. ARMv5TE coprocessor extensions
18.3.1. FMDRR
18.3.2. FMRRD
18.3.3. FMSRR
18.3.4. FMRRS
18.4. VFP11 system registers
18.4.1. Floating-Point System ID Register, FPSID
18.4.2. Floating-Point Status and Control Register, FPSCR
18.4.3. Floating-point exception register, FPEXC
18.4.4. Instruction registers, FPINST and FPINST2
18.4.5. Media and VFP Feature Register 0
18.4.6. Media and VFP Feature Register 1
19. VFP Instruction Execution
19.1. About instruction execution
19.2. Serializing instructions
19.3. Interrupting the VFP11 coprocessor
19.4. Forwarding
19.5. Hazards
19.6. Operation of the scoreboards
19.6.1. Scoreboard operation when an instruction bounces
19.6.2. Single-precision source register locking
19.6.3. Single-precision source register clearing
19.6.4. Double-precision source register locking
19.6.5. Double-precision source register clearing
19.7. Data hazards in full-compliance mode
19.7.1. Status register RAW hazard example
19.7.2. Load multiple-CDP RAW hazard example
19.7.3. Load multiple-short vector CDP RAW hazard example
19.7.4. CDP-CDP RAW hazard example
19.7.5. Short vector CDP-load multiple WAR hazard example
19.8. Data hazards in RunFast mode
19.8.1. Short vector CDP-load multiple WAR hazard example
19.9. Resource hazards
19.9.1. Load multiple-load-CDP resource hazard example
19.9.2. Load multiple-short vector CDP resource hazard example
19.9.3. Short vector CDP-CDP resource hazard example
19.10. Parallel execution
19.11. Execution timing
20. VFP Exception Handling
20.1. About exception processing
20.2. Bounced instructions
20.2.1. Potential or actual exception that the VFP11 coprocessor cannot handle
20.2.2. Potential or actual exception with the exception enable bit set
20.3. Support code
20.3.1. Illegal instructions
20.4. Exception processing
20.4.1. Determination of the trigger instruction
20.4.2. Exception processing for CDP scalar instructions
20.4.3. Exception processing for CDP short vector instructions
20.4.4. Examples of exception detection for vector instructions
20.5. Input Subnormal exception
20.5.1. Exception enabled
20.5.2. Exception disabled
20.6. Invalid Operation exception
20.6.1. Exception enabled
20.6.2. Exception disabled
20.7. Division by Zero exception
20.7.1. Exception enabled
20.7.2. Exception disabled
20.8. Overflow exception
20.8.1. Exception enabled
20.8.2. Exception disabled
20.9. Underflow exception
20.9.1. Exception enabled
20.9.2. Exception disabled
20.10. Inexact exception
20.10.1. Exception enabled
20.10.2. Exception disabled
20.11. Input exceptions
20.12. Arithmetic exceptions
20.12.1. FADD and FSUB
20.12.2. FCMP, FCMPZ, FCMPE, and FCMPEZ
20.12.3. FMUL and FNMUL
20.12.4. FMAC, FMSC, FNMAC, and FNMSC
20.12.5. FDIV
20.12.6. FSQRT
20.12.7. FCPY, FABS, and FNEG
20.12.8. FCVTDS and FCVTSD
20.12.9. FUITO and FSITO
20.12.10. FTOUI, FTOUIZ, FTOSI, and FTOSIZ
A. Signal Descriptions
A.1. AXI interface signals
A.1.1. Master port 0
A.1.2. Master port 1
A.2. Interrupt lines
A.3. Debug interface
A.4. MBIST interface
A.5. Power control interface
A.6. Miscellaneous signals
A.7. Scan test signals
A.8. ETM interface signals
A.9. Parity signals
B. AC Characteristics
B.1. MPCore timing
B.2. MPCore signal timing parameters
B.2.1. Registered signals
B.2.2. Unregistered signals
C. MBIST Controller and Dispatch Unit
C.1. About MBIST
C.2. MBIST controller and MBIST dispatch unit
C.2.1. MBIST Instruction Register
C.3. MBIST controller
C.4. MBIST dispatch unit
C.4.1. Address scrambler
C.5. MBIST signal descriptions
C.5.1. MBIST tester and MBIST controller signals
C.5.2. Controller and dispatch unit signals
C.5.3. MBIST dispatch unit and MPCore signals
C.6. Shift register and fail datalog format
C.7. Fail data log
C.8. Testing RAM
C.9. Testing MP11 CPU RAMs
C.9.1. Testing MP11 Dside data RAM
C.9.2. Testing MP11 Dside tag RAM
C.9.3. Testing MP11 Iside data RAM
C.9.4. Testing MP11 Iside tag RAM
C.9.5. Testing MP11 data dirty RAM
C.9.6. Testing MP11 TLB RAM
C.9.7. Testing MP11 BTAC RAM
C.10. Testing MP11 SCU RAM
C.11. Test patterns
D. Scan chain ordering with RVI
D.1. Scan chain ordering with RVI
E. IEM
E.1. Purpose of IEM
E.1.1. Structure of IEM
E.1.2. Operation of IEM
E.1.3. Use of IEM
E.2. About AXI register slices
F. Revisions
Glossary

List of Figures

1. Key to timing diagram conventions
1.1. ARM11 MPCore processor block diagram
1.2. MP11 CPU pipeline stages
1.3. Typical operations in pipeline stages
1.4. Typical ALU operation
1.5. Typical multiply operation
1.6. Progression of an LDR/STR operation
1.7. Progression of an LDM/STM operation
1.8. Progression of an LDR that misses
2.1. Big-endian addresses of bytes within words
2.2. Little-endian addresses of bytes within words
2.3. Register organization in ARM state
2.4. MPCore register set showing banked registers
2.5. Register organization in Thumb state
2.6. ARM state and Thumb state registers relationship
2.7. Program status register
3.1. CP15 MRC and MCR bit pattern
3.2. Main ID Register format
3.3. Cache Type Register format
3.4. TLB Type Register format
3.5. CPU ID Register format
3.6. ID_PFR0 format
3.7. ID_PFR1 format
3.8. ID_DFR0 format
3.9. Memory Model Feature Register 0 format
3.10. Memory Model Feature Register 1 format
3.11. Memory Model Feature Register 2 format
3.12. Memory Model Feature Register 3 format
3.13. Instruction Set Attributes Register 0 format
3.14. Instruction Set Attributes Register 1 format
3.15. Instruction Set Attributes Register 2 format
3.16. Instruction Set Attributes Register 3 format
3.17. Instruction Set Attributes Register 4 format
3.18. Control Register format
3.19. Auxiliary Control Register format
3.20. Coprocessor Access Control Register format
3.21. Translation Table Base Register 0 format
3.22. Translation Table Base Register 1 format
3.23. Translation Table Base Control Register format
3.24. Domain Access Control Register format
3.25. Data Fault Status Register format
3.26. Instruction Fault Status Register format
3.27. Register 7 Set/Way format
3.28. CP15 Register c7 MVA format
3.29. CP15 c7 MVA format for Flush Branch Target Cache Entry operation
3.30. VA to PA register format
3.31. PA Register aborted translation
3.32. PA Register successful translation
3.33. TLB Operations Register Virtual Address format
3.34. TLB Operations Register ASID format
3.35. Data Cache Lockdown Register format
3.36. TLB Lockdown Register format
3.37. FCSE PID Register format
3.38. Address mapping using CP15 c13
3.39. Context ID Register format
3.40. Thread ID Registers format
3.41. Performance Monitor Control Register format
3.42. TLB Debug Control Register format
3.43. Lockdown TLB index format
3.44. TLB VA Register format
3.45. Memory space identifier format
3.46. TLB PA Register format
3.47. TLB Attributes Register format
4.1. Load unsigned byte
4.2. Load signed byte
4.3. Store byte
4.4. Load unsigned halfword, little-endian
4.5. Load unsigned halfword, big-endian
4.6. Load signed halfword, little-endian
4.7. Load signed halfword, big-endian
4.8. Store halfword, little-endian
4.9. Store halfword, big-endian
4.10. Load word, little-endian
4.11. Load word, big-endian
4.12. Store word, little-endian
4.13. Store word, big-endian
5.1. Translation table managed TLB fault checking sequence 1
5.2. Translation table managed TLB fault checking sequence 2
5.3. Backwards-compatible first-level descriptor format
5.4. Backwards-compatible second-level descriptor format
5.5. Backwards-compatible section, supersection, and page translation
5.6. ARMv6 first-level descriptor formats with subpages enabled
5.7. ARMv6 first-level descriptor formats with subpages disabled
5.8. ARMv6 second-level descriptor format
5.9. ARMv6 section, supersection, and page translation
5.10. Creating a first-level descriptor address
5.11. Translation for a 1MB section, ARMv6 format
5.12. Translation for a 1MB section, backwards-compatible format
5.13. Generating a second-level page table address
5.14. Large page table walk, ARMv6 format
5.15. Large page table walk, backwards-compatible format
5.16. 4KB small page or 1KB small subpage translations, backwards-compatible
5.17. 4KB extended small page translations, ARMv6 format
5.18. 4KB extended small page or 1KB extended small subpage translations, backwards‑compatible
7.1. Level 1 data side memory system block diagram
7.2. Dynamic branch prediction and instruction cache lookup blocks
8.1. Exclusive monitor state machine
8.2. ACLKEN signal timing
9.1. SCU Control Register format
9.2. SCU Configuration Register format
9.3. SCU MP11 CPU Status Register
9.4. SCU Invalidate All Register format
9.5. SCU Performance Monitor Control Register format
9.6. Performance Monitor Event Register 0 bit format
9.7. Performance Monitor Event Register 1 bit format
9.8. Timer Control Register format
9.9. Timer Interrupt Status Register format
9.10. Watchdog Control Register format
9.11. Watchdog Interrupt Status Register format
9.12. Watchdog Reset Status Register format
10.1. Interrupt Distributor block diagram
10.2. Interrupt Distributor Control Register format
10.3. Interrupt Controller Type Register format
10.4. Interrupt Priority Registers format
10.5. Interrupt CPU Targets Registers format
10.6. Interrupt Configuration Registers format
10.7. Software Interrupt Register format
10.8. CPU Interface Control Register format
10.9. Priority Mask Register format
10.10. Binary Point Register format
10.11. Interrupt Acknowledge Register format
10.12. Running Priority Register format
11.1. ARM11 MPCore processor power management
12.1. Typical debug system
12.2. Debug ID Register format
12.3. Debug Status and Control Register format
12.4. Core restarted bit and core halted bit
12.5. DTR format
12.6. Vector Catch Register format
12.7. Breakpoint Control Registers format
12.8. Watchpoint Control Registers format
13.1. JTAG DBGTAP state machine diagram
13.2. Bypass register bit order
13.3. Device ID code register bit order
13.4. Instruction Register bit order
13.5. Scan Chain Select Register bit order
13.6. Scan chain 0 bit order
13.7. Scan chain 1 bit order
13.8. Scan chain 4 bit order
13.9. Scan chain 5 bit order, EXTEST selected
13.10. Scan chain 5 bit order, INTEST selected
13.11. Scan chain 7 bit order
13.12. Behavior of the ITRsel IR instruction
14.1. ETMCPADDRESS encoding
16.1. FMAC pipeline
16.2. DS pipeline
16.3. LS pipeline
17.1. Single-precision data format
17.2. Double-precision data format
17.3. Register file access
17.4. Register banks
18.1. FMDRR instruction format
18.2. FMRRD instruction format
18.3. FMSRR instruction format
18.4. FMRRS instruction format
18.5. Floating-Point System ID Register
18.6. Floating-Point Status and Control Register
18.7. Floating-Point Exception Register
18.8. Media and VFP Feature Register 0 format
18.9. Media and VFP Feature Register 1 format
B.1. Target timing parameters for unregistered signals
C.1. MBIST block diagram
C.2. Data mapping for MBIST
C.3. Dside tag RAM mapping
C.4. Iside data array mapping
C.5. Iside tag RAM MBISTDOUT mapping
C.6. Data dirty RAM mapping
C.7. TLB RAM organization with four MP11 CPUs
C.8. TLB mapping
C.9. BTAC mapping
C.10. SCU RAM array organization
C.11. SCU tag RAM mapping
E.1. IEM structure
E.2. AXI register slices and level shifters
E.3. IEC request/acknowledge interface
E.4. AXI write channel

List of Tables

1.1. Double-precision VFP operations
1.2. Flush-to-zero mode
1.3. Configurable options for the ARM11 MPCore processor
1.4. Default configuration for the ARM11 MPCore processor
2.1. Address types in an MPCore system
2.2. Register mode identifiers
2.3. GE[3:0] settings
2.4. PSR mode bit values
2.5. Exception entry and exit
2.6. Configuration of exception vector address locations
2.7. Exception vectors
3.1. CP15 register functions
3.2. Summary of CP15 registers and operations
3.3. Main ID Register bit functions
3.4. Cache Type Register bit functions
3.5. TLB Type Register bit functions
3.6. ID_PFRO bit functions
3.7. ID_PFR1 bit functions
3.8. Debug Feature Register 0 bit functions
3.9. Memory Model Feature Register 0 bit functions
3.10. ID_MMFR1 bit functions
3.11. ID_MMFR2 bit functions
3.12. ID_MMFR3 bit functions
3.13. Instruction Set Attributes Register 0 bit functions
3.14. Instruction Set Attributes Register 1 bit functions
3.15. Instruction Set Attributes Register 2 bit functions
3.16. Instruction Set Attributes Register 3 bit functions
3.17. Instruction Set Attributes Register 4 bit functions
3.18. CFGEND, EE, U, and E bit values
3.19. Endianness and alignment control options
3.20. Control Register bit functions
3.21. Auxiliary Control Register bit functions
3.22. Coprocessor access rights
3.23. Translation Table Base Register 0 bit functions
3.24. Translation Table Base Register 1 bit functions
3.25. Values of N for Translation Table Base Register 0
3.26. Encoding of domain bits in CP15 c3
3.27. Data Fault Status Register bit functions
3.28. Instruction Fault Status Register bit functions
3.29. Cache operation functions
3.30. Bit fields for Set/Way operations using CP15 c7
3.31. Cache size and S parameter dependency
3.32. PA Register bit functions
3.33. TLB Operations Register instructions
3.34. CRm values for TLB Operations Register
3.35. Primary remapping encodings
3.36. Inner or outer region type encodings
3.37. Fields for primary region remap
3.38. Fields for normal memory region remap
3.39. Default memory regions when MMU is disabled
3.40. Performance Monitor Control Register bit functions
3.41. Performance monitoring events
3.42. Main TLB debug operations
3.43. TLB Debug Control Register bit functions
3.44. TLB lockdown operations
3.45. TLB VA Register bit functions
3.46. TLB PA Register bit functions
3.47. TLB Attributes Register bit functions
3.48. Upper subpage permissions
3.49. CP15 instruction summary
4.1. Unaligned access handling
4.2. Memory access type descriptions
4.3. Unalignment fault occurrence when access behavior is architecturally unpredictable
4.4. Mixed-endian configuration
4.5. EE bit, U bit, and E bit settings
5.1. Access permission bits encoding
5.2. Access permission bits
5.3. TEX field, and C and B bit encodings used in page table formats
5.4. Cache policy bits
5.5. Inner and Outer cache policy implementation options
5.6. New V6 TEX, CB encodings
5.7. Page attributes and memory types
5.8. Memory attributes
5.9. Memory ordering restrictions
5.10. Memory region backwards compatibility
5.11. Fault Status Register encoding
5.12. Summary of aborts
5.13. Access types from first-level descriptor bit values
5.14. Access types from second-level descriptor bit values
5.15. CP15 register functions
8.1. AXI master interface attributes
8.2. Core mode and APROT values
8.3. AWUSER pins and meanings
9.1. MPCore private memory region
9.2. SCU register definition
9.3. SCU Control Register bit assignments
9.4. SCU Configuration Register bit assignments
9.5. SCU CPU Status Register bit assignments
9.6. SCU Invalidate All Register bit assignment
9.7. MP11 CPUs and counters
9.8. Performance Monitor Control Register bit assignments
9.9. Event definitions
9.10. Performance Monitor Event Register 0 bit assignments
9.11. Performance Monitor Event Register 1 bit assignments
9.12. Timer and watchdog registers
9.13. Timer Control Register bit assignments
9.14. Watchdog Control Register bit assignments
10.1. Distributed Interrupt controller programmer’s model
10.2. Interrupt Controller Type Register bit assignments
10.3. Interrupt line encodings for bits 1 and 0
10.4. Software Interrupt Register bit assignments
10.5. MP11 CPU Interrupt Interface Registers
10.6. Priority Mask Register bit assignments
10.7. Binary point bit values assignment
10.8. Interrupt Acknowledge Register bit assignments
11.1. Reset modes
11.2. MP11 CPU power modes
12.1. Terms used in register descriptions
12.2. CP14 debug register map
12.3. Debug ID Register bit functions
12.4. Debug Status and Control Register bit functions
12.5. Data Transfer Register bit functions
12.6. Vector Catch Register bit functions
12.7. MPCore breakpoint and watchpoint registers
12.8. Breakpoint Value Registers bit functions
12.9. Breakpoint Control Registers bit functions
12.10. Meaning of BCR[21:20] bits
12.11. Watchpoint Value Registers bit functions
12.12. Watchpoint Control Registers bit functions
12.13. CP14 debug instructions
12.14. Debug instruction execution
12.15. Behavior of the processor on debug events
12.16. Setting of CP15 registers on debug events
12.17. Values in the link register after exceptions
12.18. Read PC value after debug state entry
13.1. Supported public instructions
13.2. Scan chain 7 register map
14.1. Instruction interface signals
14.2. ETMIACTL[17:0]
14.3. Data address interface signals
14.4. ETMDACTL[17:0]
14.5. Data value interface signals
14.6. ETMDRCTL[3:0]
14.7. ETMPADV[2:0]
14.8. Coprocessor interface signals
14.9. Other connections
15.1. Definition of cycle timing terms
15.2. Pipeline stages
15.3. Register interlock examples
15.4. Data Processing instruction cycle timing behavior if destination is not PC
15.5. Data processing instruction cycle timing behavior if destination is the PC
15.6. QADD, QDADD, QSUB, and QDSUB instruction cycle timing behavior
15.7. ARMv6 media data processing instructions cycle timing behavior
15.8. ARMv6 sum of absolute differences instruction timing behavior
15.9. Example interlocks
15.10. Example multiply instruction cycle timing behavior
15.11. Branch instruction cycle timing behavior
15.12. Processor state updating instructions cycle timing behavior
15.13. Cycle timing behavior for stores and loads, other than loads to the PC
15.14. Cycle timing behavior for loads to the PC
15.15. <addr_md_1cycle> and <addr_md_2cycle> LDR example instruction
15.16. Load and store double instructions cycle timing behavior
15.17. <addr_md_1cycle> and <addr_md_2cycle> LDRD example instruction
15.18. Load and store multiples, other than load multiples including the PC
15.19. Cycle timing behavior of load multiples, where the PC is in the register list
15.20. RFE and SRS instructions cycle timing behavior
15.21. Synchronization instructions cycle timing behavior
15.22. Coprocessor instructions cycle timing behavior
15.23. SWI, BKPT, Undefined, Prefetch Aborted instructions cycle timing behavior
17.1. VFP11 MCR instructions
17.2. VFP11 MRC instructions
17.3. VFP11 MCRR instructions
17.4. VFP11 MRRC instructions
17.5. Single‑precision data memory images and byte addresses
17.6. Double‑precision data memory images and byte addresses
17.7. Single‑precision three-operand register usage
17.8. Single-precision two-operand register usage
17.9. Double-precision three-operand register usage
17.10. Double-precision two-operand register usage
18.1. Default NaN values
18.2. QNaN and SNaN handling
18.3. VFP11 system registers
18.4. Accessing VFP11 system registers
18.5. FPSID bit fields
18.6. Encoding of the Floating-Point Status and Control Register
18.7. Vector length and stride combinations
18.8. Encoding of the Floating-Point Exception Register
18.9. Media and VFP Feature Register 0 bit functions
18.10. Media and VFP Feature Register 1 bit functions
19.1. Single-precision source register locking
19.2. Single-precision source register clearing
19.3. Double-precision source register locking
19.4. Double-precision source register clearing for one-cycle instructions
19.5. Double-precision source register clearing for two-cycle instructions
19.6. FCMPS-FMSTAT RAW hazard
19.7. FLDM-FADDS RAW hazard
19.8. FLDM-short vector FADDS RAW hazard
19.9. FMULS-FADDS RAW hazard
19.10. Short vector FMULS-FLDMS WAR hazard
19.11. Short vector FMULS-FLDMS WAR hazard in RunFast mode
19.12. FLDM-FLDS-FADDS resource hazard
19.13. FLDM-short vector FMULS resource hazard
19.14. Short vector FDIVS-FADDS resource hazard
19.15. Parallel execution in all three pipelines
19.16. Throughput and latency cycle counts for VFP11 instructions
20.1. Exceptional short vector FMULD followed by load/store instructions
20.2. Exceptional short vector FADDS with a FADDS in the pretrigger slot
20.3. Exceptional short vector FADDD with an FMACS trigger instruction
20.4. Possible Invalid Operation exceptions
20.5. Default results for invalid conversion inputs
20.6. Rounding mode overflow results
20.7. LSA and USA determination
20.8. FADD family bounce thresholds
20.9. FMUL family bounce thresholds
20.10. FDIV bounce thresholds
20.11. FCVTSD bounce thresholds
20.12. Single-precision float-to-integer bounce thresholds and stored results
20.13. Double-precision float-to-integer bounce thresholds and stored results
A.1. Master port 0 read address channel
A.2. Master port 0 read channel
A.3. Master port 0 write address channel
A.4. Master port 0 write channel
A.5. Master port 0 write response channel
A.6. Master port 1 read address channel
A.7. Master port 1 read channel
A.8. Master port 1 write address channel
A.9. Master port 1 write channel
A.10. Master port 1 write response channel
A.11. Interrupt line signals
A.12. Debug interface signals
A.13. MBIST interface signals
A.14. Power control interface signals
A.15. Miscellaneous signals
A.16. Scan test signals
A.17. ETM interface signals
A.18. Parity signals
C.1. MBIST tester and MBIST controller signals
C.2. MBISTRESULT signal descriptions
C.3. MBISTTX bus bit assignments
C.4. MBISTR[5:0]
C.5. MBIST dispatch unit signals
C.6. CPU mappings to MBISTOUT bits
C.7. MBISTCE encodings
C.8. MBIST Instruction Register bit assignments
C.9. MBIST Dispatch Unit bit assignments
C.10. Data log bit assignments
C.11. RTL options
C.12. RAM accesses using MBISTCE
C.13. MBIST signals and ways
C.14. Data cache size and Dside data RAM arrays
C.15. MBIST signals and ways for Dside tag RAM
C.16. Data cache size and tag RAM arrays
C.17. MBIST enable signals and Iside data RAM bocks
C.18. Iside cache size and data RAM arrays
C.19. MBIST signals and ways for Iside tag RAM
C.20. Cache sizes and iside tag RAM arrays
C.21. Cache sizes and Data dirty RAMs arrays
C.22. TLB RAMs and MBIST signals
C.23. Enabling SCU RAM arrays
C.24. SCU RAM arrays and data cache sizes
C.25. Instruction Register values and MBIST test patterns
D.1. RVI ordering, MP11 CPUID, and physical JTAG positions
D.2. One additional item in the scan chain
D.3. Two additional items in the scan chain
F.1. Differences between issue E and issue F

Proprietary Notice

Words and logos marked with ® or ™ are registered trademarks or trademarks of ARM Limited in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Figure 13.1 reprinted with permission from IEEE Std. 1149.1-1990, IEEE Standard Test Access Port and Boundary-Scan Architecture Copyright 2002, 2003, by IEEE. The IEEE disclaims any responsibility or liability resulting from the placement and use in the described manner.

Some material in this document is based on IEEE Standard for Binary Floating-Point Arithmetic, ANSI/IEEE Std 754-1985. The IEEE disclaims any responsibility or liability resulting from the placement and use in the described manner.

Where the term ARM is used it means “ARM or any of its subsidiaries as appropriate”.

Confidentiality Status

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Product Status

The information in this document is final, that is for a developed product.

Revision History
Revision A02 February 2005First release for r0p1
Revision B14 September 2005First release for r0p2
Revision C16 December 2005First release for r0p3
Revision D11 August 2006First release for r1p0
Revision E14 February 2008Second release for r1p0
Revision F15 October 2008First release for r2p0
Copyright © 2005, 2006, 2008. All rights reserved.ARM DDI 0360F
Non-Confidential