| Copyright © 2009 ARM Limited. All rights reserved. | ARM DDI 0363E |
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Faults can occur on instruction fetches for the following reasons:
MPU background fault
MPU permission fault
External AXI slave error (SLVERR)
External AXI decode error (DECERR)
Cache parity or ECC error
TCM parity or ECC error
TCM external error
TCM external retry request
Breakpoints, and vector capture events.
Faults can occur on data accesses for the following reasons:
MPU background fault
MPU permission fault
MPU alignment fault
External AXI slave error (SLVERR)
External AXI decode error (DECERR)
Cache parity or ECC error
TCM parity or ECC error
TCM external error
TCM external retry request
Watchpoints.
Fault handling is described in:
| Copyright © 2009 ARM Limited. All rights reserved. | ARM DDI 0363E |
| Non-Confidential | |
| PDF version | |
| Home > Level One Memory System > Fault handling |