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The processor reports the status and address of faults that occur during its operation. For both data and instruction faults there are two Fault Status Registers (FSRs) and one Fault Address Register (FAR).
Fields within the Data and Instruction FSRs indicate the priority and source of a fault and the validity of the address in the corresponding FAR. Table 4.27 shows this encoding for the FSRs.
Table 4.27. Fault Status Register encodings
| Priority | Sources | FSR [10,3:0] | FAR |
|---|---|---|---|
| Highest | Alignment | 0b00001 | Valid |
| Background | 0b00000 | Valid | |
| Permission | 0b01101 | Valid | |
| Precise External Abort | 0b01000 | Valid | |
| Imprecise External Abort | 0b10110 | Unpredictable | |
| Precise Parity/ECC Error | 0b11001 | Valid | |
| Imprecise Parity/ECC Error | 0b11000 | Unpredictable | |
| Lowest | Debug Event | 0b00010 | Unchanged |
All other encodings for these FSR bits are Reserved.
The Data Fault Status Register (DFSR) holds status information regarding the source of the last data abort.
The Data Fault Status Register is:
a read/write register
accessible in Privileged mode only.
Figure 4.31 shows the bit arrangement in the Data Fault Status Register.
Table 4.28 shows how the bit values correspond with the Data Fault Status Register functions.
Table 4.28. Data Fault Status Register bit functions
Bits | Field | Function |
|---|---|---|
[31:13] | Reserved | SBZ. |
[12] | SD | Distinguishes between an AXI Decode or Slave error on an external abort. This bit is only valid for external aborts. For all other aborts types of abort, this bit is set to zero: 0 = AXI Decode error (DECERR) caused the abort 1 = AXI Slave error (SLVERR, or OKAY in response to exclusive read transaction) caused the abort. |
[11] | RW | Indicates whether a read or write access caused an abort: 0 = read access caused the abort 1 = write access caused the abort. |
[10][a] | S | Part of the Status field. |
[9:8] | - | Always read as 0. Writes ignored. |
[7:4] | Domain | SBZ. This is because domains are not implemented in this processor. |
[3:0][a] | Status | Indicates the type of fault generated. To determine the data fault, you must use bit [12] and bit [10] in conjunction with bits [3:0]. |
[a] For more information on how these bits are used in reporting faults, see Table 4.27. | ||
To use the DFSR read or write CP15 with:
MRC p15, 0, <Rd>, c5, c0, 0 ; Read Data Fault Status Register
MCR p15, 0, <Rd>, c5, c0, 0 ; Write Data Fault Status Register
The Instruction Fault Status Register (IFSR) holds status information regarding the source of the last instruction abort.
The Instruction Fault Status Register is:
a read/write register
accessible in Privileged mode only.
Figure 4.32 shows the bit arrangement in the Instruction Fault Status Register.
Table 4.29 shows how the bit values correspond with the Instruction Fault Status Register functions.
Table 4.29. Instruction Fault Status Register bit functions
| Bits | Field | Function |
|---|---|---|
| [31:13] | Reserved | SBZ. |
| [12] | SD | Distinguishes between an AXI Decode or Slave error on an external abort. This bit is only valid for external aborts. For all other aborts types of abort, this bit is set to zero: 0 = AXI Decode error (DECERR) caused the abort 1 = AXI Slave error (SLVERR) caused the abort. |
| [11] | Reserved | SBZ. |
| [10][a] | S | Part of the Status field. |
| [9:8] | Reserved | SBZ. |
| [7:4] | Domain | SBZ. This is because domains are not implemented in this processor. |
| [3:0][a] | Status | Indicates the type of fault generated. To determine the instruction fault, bit [12] and bit [10] must be used in conjunction with bits [3:0]. |
[a] For more information on how these bits are used in reporting faults, see Table 4.27. | ||
To access the IFSR read or write CP15 with:
MRC p15, 0, <Rd>, c5, c0, 1 ; Read Instruction Fault Status Register
MCR p15, 0, <Rd>, c5, c0, 1 ; Write Instruction Fault Status Register
There are two auxiliary fault status registers:
the Auxiliary Data Fault Status Register (ADFSR)
the Auxiliary Instruction Fault Status Register (AIFSR).
These registers provide additional information about data and instruction parity, ECC, and external TCM errors.
The auxiliary fault status registers are:
read/write registers
accessible in Privileged mode only.
Figure 4.33 shows the bit arrangement in the auxiliary fault status registers.
Table 4.30 shows how the bit values correspond with the auxiliary fault status register functions.
Table 4.30. ADFSR and AIFSR bit functions
| Bits | Field | Function |
|---|---|---|
| [31:28] | Reserved | SBZ. |
| [27:24] | CacheWay[a] | The value returned in this field indicates the cache way or ways in which the error occurred. |
| [23:22] | Side | The value returned in this field indicates the source of the error. Possible values are: b00 = Cache or AXI-master interface b01 = ATCM b10 = BTCM b11 = Reserved. |
| [21] | Recoverable error | The value returned in this field indicates if the error is recoverable. 0 = Unrecoverable error. 1 = Recoverable error. This includes all correctable parity/ECC errors and recoverable TCM external errors. |
| [20:14] | Reserved | SBZ. |
| [13:5] | Index[b] | This field returns the index value for the access giving the error. |
| [4:0] | Reserved | SBZ. |
[a] This field is only valid for data cache store parity/ECC errors, otherwise it is Unpredictable. [b] This field is only valid for data cache store parity/ECC errors. On the AIFSR, and for TCM accesses, this field SBZ. | ||
To access the auxiliary fault status registers, read or write CP15 with:
MCR p15, 0, <Rd>, c5, c1, 0 ; Write Auxiliary Data Fault Status Register
MRC p15, 0, <Rd>, c5, c1, 0 ; Read Auxiliary Data Fault Status Register
MCR p15, 0, <Rd>, c5, c1, 1 ; Write Auxiliary Instruction Fault Status Register
MRC p15, 0, <Rd>, c5, c1, 1 ; Read Auxiliary Instruction Fault Status Register
The contents of an auxiliary fault status register are only valid when the corresponding Data or Instruction Fault Status Register indicates that a parity error has occurred. At other times the contents of the auxiliary fault status registers are Unpredictable.
The Data Fault Address Register (DFAR) holds the address of the fault when a precise abort occurs.
The DFAR is:
a read/write register
accessible in Privileged mode only.
The Data Fault Address Register bits [31:0] contain the address where the precise abort occurred.
To access the DFAR read or write CP15 with:
MRC p15, 0, <Rd>, c6, c0, 0 ; Read Data Fault Address Register
MCR p15, 0, <Rd>, c6, c0, 0 ; Write Data Fault Address Register
A write to this register sets the DFAR to the value of the data written. This is useful for a debugger to restore the value of the DFAR.
The processor also updates the DFAR on debug exception entry because of watchpoints. See Effect of debug exceptions on CP15 registers and WFAR for more information.
The purpose of the Instruction Fault Address Register (IFAR) is to hold the address of instructions that cause a prefetch abort.
The IFAR is:
a read/write register
accessible in Privileged mode only.
The Instruction Fault Address Register bits [31:0] contain the Instruction Fault address.
To access the IFAR read or write CP15 with:
MRC p15, 0, <Rd>, c6, c0, 2 ; Read Instruction Fault Address Register
MCR p15, 0, <Rd>, c6, c0, 2 ; Write Instruction Fault Address Register
A write to this register sets the IFAR to the value of the data written. This is useful for a debugger to restore the value of the IFAR.
| Copyright © 2009 ARM Limited. All rights reserved. | ARM DDI 0363E |
| Non-Confidential | |
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