| Copyright © 2009 ARM Limited. All rights reserved. | ARM DDI 0363E |
| Non-Confidential | |
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| Home > Level Two Interface > Accessing RAMs using the AXI slave interface > Cache RAM access |
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This section contains the following:
The memory maps for the data and instruction caches have the same format. Because the instruction cache does not have a dirty RAM, accesses to it generate the SLVERR error response.
Table 9.29, Table 9.30, and Table 9.31 show the chip-select decodes for selecting the cache RAMs in the processor.
Table 9.29. Cache RAM chip-select decode
| Inputs | RAM selected | |
|---|---|---|
| ARUSERS[3:0] | ARADDRS[22:19] | |
| 0100 | 0000 | Instruction cache data RAM |
| 0100 | 0001 | Instruction cache tag RAM |
| 0100 | 0010 | Not used, generates an error |
| 0100 | 0011 | Not used, generates an error |
| 0100 | ARADDRS[22:21] != 00 | Not used, generates an error |
| 1000 | 0000 | Data cache data RAM |
| 1000 | 0001 | Data cache tag RAM |
| 1000 | 0010 | Data cache dirty RAM |
| 1000 | 0011 | Not used, generates an error |
| 1000 | ARADDRS[22:21] != 00 | Not used, generates an error |
Table 9.30. Cache tag/valid RAM bank/address decode
| Inputs | RAM bank selected | Cache way |
|---|---|---|
| ARADDRS[18:15] | ||
| 0001 | Bank 0 | 0 |
| 0010 | Bank 1 | 1 |
| 0100 | Bank 2 | 2 |
| 1000 | Bank 3 | 3 |
Table 9.31. Cache data RAM bank/address decode
| Inputs | RAM bank selected | |
|---|---|---|
| ARADDRS[18:15] | ARADDRS[3] | |
| 0001 | 0 | Bank 0 |
| 0001 | 1 | Bank 1 |
| 0010 | 0 | Bank 2 |
| 0010 | 1 | Bank 3 |
| 0100 | 0 | Bank 4 |
| 0100 | 1 | Bank 5 |
| 1000 | 0 | Bank 6 |
| 1000 | 1 | Bank 7 |
You can only access the cache RAMs using 32-bit or 64-bit AXI transfers. Using an 8-bit or a 16-bit transfer size generates a SLVERR error response.
The following tables shows the data formats for cache data RAM accesses:
Table 9.32 shows the format when neither parity nor ECC is implemented
Table 9.33 shows the format when parity is implemented
Table 9.34 shows the instruction cache format when ECC is implemented
Table 9.35 shows the data cache format when ECC is implemented.
Table 9.32. Data format, instruction cache and data cache, no parity and no ECC
| Data bit | Description |
|---|---|
| [63:48] | Not used, read-as-zero |
| [47:32] | Data value, [31:16] or [63:48] |
| [31:16] | Not used, read-as-zero |
| [15:0] | Data value, [15:0] or [47:32] |
Table 9.33. Data format, instruction cache and data cache, with parity
| Data bit | Description |
|---|---|
| [63:50] | Not used, read-as-zero |
| [49] | Parity bit for data value [31:24] or [63:56] |
| [48] | Parity bit for data value [23:16] or [55:48] |
| [47:32] | Data value, [31:16] or [63:48] |
| [31:18] | Not used, read-as-zero |
| [17] | Parity bit for data value [15:8] or [47:40] |
| [16] | Parity bit for data value [7:0] or [39:32] |
| [15:0] | Data value, [15:0] or [47:32] |
Table 9.34. Data format, instruction cache, with ECC
| Data bit | Description |
|---|---|
| [63:52] | Not used, read-as-zero |
| [51:48] | Upper or lower half of the ECC 64 code [a] |
| [47:32] | Data value, [31:16] or [63:48] |
| [31:20] | Not used, read-as-zero |
| [19:16] | Upper or lower half of the ECC 64 code [b] |
| [15:0] | Data value, [15:0] or [47:32] |
[a] If accessing bits [31:16] of the data, bits [51:48] hold the lower half of the ECC code. If accessing bits [63:48] of the data, bits [51:48] hold the upper half of the ECC code. [b] If accessing bits [15:0] of the data, bits [19:16] hold the lower half of the ECC code. If accessing bits [47:32] of the data, bits [19:16] hold the upper half of the ECC code. | |
Table 9.35. Data format, data cache, with ECC
| Data bit | Description |
|---|---|
| [63:55] | Not used, read-as-zero |
| [54:48] | ECC 32 code [a] |
| [47:32] | Data value, [31:16] or [63:48] |
| [31:23] | Not used, read-as-zero |
| [22:16] | ECC 32 code |
| [15:0] | Data value [15:0] or [47:32] |
[a] For a 64 bit access, the ECC bits are duplicated in bits [22:16] and bits [54:48], and the two copies are identical. For a 32 bit access, the ECC bits refer to the whole 32 bit data value, even though only 16 bits of data are accessed. | |
The following tables show the data formats for tag RAM accesses:
Table 9.36 shows the format for read accesses when neither parity nor ECC is implemented
Table 9.37 shows the format for read accesses when parity is implemented
Table 9.38 shows the format for read accesses when ECC is implemented
Table 9.39 shows the format for write accesses when neither parity nor ECC is implemented
Table 9.40 shows the format for write accesses when parity is implemented
Table 9.41 shows the format for write accesses when ECC is implemented.
Table 9.36. Tag register format for reads, no parity or ECC
| Data bit | Description |
|---|---|
| [63:55] | Not used, read-as-zero |
| [54] | Valid, way 2/3 |
| [53:32] | Tag value, way 2/3 |
| [31:23] | Not used, read-as-zero |
| [22] | Valid, way 0/1 |
| [21:0] | Tag value, way 0/1 |
Table 9.37. Tag register format for reads, with parity
| Data bit | Description |
|---|---|
| [63:56] | Not used, read-as-zero |
| [55] | Parity, way 2/3 |
| [54] | Valid, way 2/3 |
| [53:32] | Tag value, way 2/3 |
| [31:24] | Not used, read-as-zero |
| [23] | Parity, way 0/1 |
| [22] | Valid, way 0/1 |
| [21:0] | Tag value, way 0/1 |
Table 9.38. Tag register format for reads, with ECC
| Data bit | Description |
|---|---|
| [63:62] | Not used, read-as-zero |
| [61:55] | ECC, way 2/3 |
| [54] | Valid, way 2/3 |
| [53:32] | Tag value, way 2/3 |
| [31:30] | Not used, read-as-zero |
| [29:23] | ECC, way 0/1 |
| [22] | Valid, way 0/1 |
| [21:0] | Tag value, way 0/1 |
Table 9.39. Tag register format for writes, no parity or ECC
| Data bit | Description |
|---|---|
| [63:23] | Not used, read-as-zero |
| [22] | Valid, all ways |
| [21:0] | Tag value, all ways |
Table 9.40. Tag register format for writes, with parity
| Data bit | Description |
|---|---|
| [63:24] | Not used, read-as-zero |
| [23] | Parity. all ways |
| [22] | Valid, all ways |
| [21:0] | Tag value, all ways |
Table 9.41. Tag register format for writes, with ECC
| Data bit | Description |
|---|---|
| [63:30] | Not used, read-as-zero |
| [29:23] | ECC, all ways |
| [22] | Valid, all ways |
| [21:0] | Tag value, all ways |
For tag RAM writes, only bits [23:0] of the data bus are used. If two tag RAMs are written at the same time, they are both written with the same data. To write only one tag RAM using the AXI Slave, select only one RAM with bits [18:15] of the address bus.
The following tables show the data format for accessing the dirty RAM:
Table 9.42 shows the format when parity is implemented, or no error scheme is implemented
Table 9.43 shows the format when ECC is implemented.
Table 9.42. Dirty register format, with parity or with no error scheme
| Data bit | Description |
|---|---|
| [63:27] | Not used, read-as-zero |
| [26:25] | Outer attributes, way 3 |
| [24] | Dirty value, way 3 |
| [23:19] | Not used, read-as-zero |
| [18:17] | Outer attributes, way 2 |
| [16] | Dirty value, way 2 |
| [15:11] | Not used, read-as-zero |
| [10:9] | Outer attributes, way 1 |
| [8] | Dirty value, way 1 |
| [7:3] | Not used, read-as-zero |
| [2:1] | Outer attributes, way 0 |
| [0] | Dirty value, way 0 |
When parity checking is enabled, all Cacheable accesses are forced to write-through. Therefore the dirty RAM is not used and does not require parity protection.
Table 9.43. Dirty register format, with ECC
| Data bit | Description |
|---|---|
| [63:31] | Not used, read-as-zero |
| [30:27] | ECC, way 3 |
| [26:25] | Outer attributes, way 3 |
| [24] | Dirty value, way 3 |
| [23] | Not used, read-as-zero |
| [22:19] | ECC, way 2 |
| [18:17] | Outer attributes, way 2 |
| [16] | Dirty value, way 2 |
| [15] | Not used, read-as-zero |
| [14:11] | ECC, way 1 |
| [10:9] | Outer attributes, way 1 |
| [8] | Dirty value, way 1 |
| [7] | Not used, read-as-zero |
| [6:3] | ECC, way 0 |
| [2:1] | Outer attributes, way 0 |
| [0] | Dirty value, way 0 |
Normally ARADDRS[18:15] is a one-hot field, and only accesses one RAM at a time.
However, if you want to access two tag RAMs, such as banks 0 and 2 or banks 1 and 3 at the same time, use:
ARADDRS[18:15] = 4'b0101 to access banks 0 and 2
ARADDRS[18:15] = 4'b1010 to access banks 1 and 3.
This enables data to be read from two tag RAMs simultaneously, and the same data to be written to two tag RAMs simultaneously. To write different data to each tag RAM, you must ensure only one tag RAM is accessed at a time.
You can access any combination of dirty RAM banks simultaneously. For example, to access all dirty RAM banks use:
ARADDRS[18:15] = 4'b1111.
If you break these rules, for example if you access tag RAM banks 0 and 1, no SLVERR response is generated, and any attempt to read or write banks in other combinations or multiple banks of other RAMs is Unpredictable.
If you attempt to read or write cache RAMs outside the physical
cache size implemented, the MSBs for that read or write access are
ignored. For example, accessing 0x10000000 or 0x00000000 addresses
in the cache RAM accesses the same physical location 0x0.
This means that such accesses are aliased and no errors are generated.
| Copyright © 2009 ARM Limited. All rights reserved. | ARM DDI 0363E |
| Non-Confidential | |
| PDF version | |
| Home > Level Two Interface > Accessing RAMs using the AXI slave interface > Cache RAM access |