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The processor implements a set of validation registers. This section describes:
The nVAL IRQ Enable Set Register enables any of the PMC Registers, PMC0-PMC2, and CCNT, to generate an interrupt request on overflow. If enabled, the interrupt request is signaled by nVALIRQ being asserted LOW.
The nVAL IRQ Enable Set Register is:
A read/write register.
Always accessible in Privileged mode. The USEREN Register determines access, see c9, User Enable Register.
Figure 4.44 shows the bit arrangement for the nVAL IRQ Enable Set Register.
Table 4.42 shows how the bit values correspond with the nVAL IRQ Enable Set Register.
Table 4.42. nVAL IRQ Enable Set Register bit functions
Bits | Field | Function |
|---|---|---|
| [31] | C | CCNT overflow IRQ request |
| [30: 3] | Reserved | UNP or SBZP |
| [2] | P2 | PMC2 overflow IRQ request |
| [1] | P1 | PMC1 overflow IRQ request |
| [0] | P0 | PMC0 overflow IRQ request |
To access the nVAL IRQ Enable Set Register, read or write CP15 with:
MRC p15, 0, <Rd>, c15, c1, 0 ; Read nVAL IRQ Enable Set Register
MCR p15, 0, <Rd>, c15, c1, 0 ; Write nVAL IRQ Enable Set Register
On reads, this register returns the current setting. On writes, interrupt requests can be enabled. If an interrupt request has been enabled it is disabled by writing to the nVAL IRQ Enable Clear Register, see c15, nVAL IRQ Enable Clear Register.
If one or more of the IRQ request fields (P2, P1, P0, and C) is enabled, and the corresponding counter overflows, then an IRQ request is indicated by nVALIRQ being asserted LOW. This signal might be passed to a system interrupt controller.
The nVAL FIQ Enable Set Register enables any of the PMC Registers, PMC0-PMC2, and CCNT, to generate an fast interrupt request on overflow. If enabled, the interrupt request is signaled by nVALFIQ being asserted LOW.
The nVAL FIQ Enable Set Register is:
A read/write register.
Always accessible in Privileged mode. The USEREN Register determines access, see c9, User Enable Register.
Figure 4.45 shows the bit arrangement for the nVAL FIQ Enable Set Register.
Table 4.43 shows how the bit values correspond with the nVAL FIQ Enable Set Register.
Table 4.43. nVAL FIQ Enable Set Register bit functions
Bits | Field | Function |
|---|---|---|
| [31] | C | CCNT overflow FIQ request |
| [30:3] | Reserved | UNP or SBZP |
| [2] | P2 | PMC2 overflow FIQ request |
| [1] | P1 | PMC1 overflow FIQ request |
| [0] | P0 | PMC0 overflow FIQ request |
To access the FIQ Enable Set Register, read or write CP15 with:
MRC p15, 0, <Rd>, c15, c1, 1 ; Read FIQ Enable Set Register
MCR p15, 0, <Rd>, c15, c1, 1 ; Write FIQ Enable Set Register
On reads, this register returns the current setting. On writes, interrupt requests can be enabled. If an interrupt request has been enabled it is disabled by writing to the FIQ Enable Clear Register, see c15, nVAL FIQ Enable Clear Register.
If one or more of the FIQ request fields (P2, P1, P0, and C) is enabled, and the corresponding counter overflows, then an FIQ request is indicated by nVALFIQ being asserted LOW. This signal can be passed to a system interrupt controller.
The nVAL Reset Enable Set Register enables any of the PMC Registers, PMC0-PMC2, and CCNT, to generate a reset request on overflow. If enabled, the reset request is signaled by nVALRESET being asserted LOW.
The nVAL Reset Enable Set Register is:
A read/write register.
Always accessible in Privileged mode. The USEREN Register determines access, see c9, User Enable Register.
Figure 4.46 shows the bit arrangement for the nVAL Reset Enable Set Register.
Table 4.44 shows how the bit values correspond with the nVAL Reset Enable Set Register.
Table 4.44. nVAL Reset Enable Set Register bit functions
Bits | Field | Function |
|---|---|---|
| [31] | C | CCNT overflow reset request |
| [30:3] | Reserved | UNP or SBZP |
| [2] | P2 | PMC2 overflow reset request |
| [1] | P1 | PMC1 overflow reset request |
| [0] | P0 | PMC0 overflow reset request |
To access the nVAL Reset Enable Set Register, read or write CP15 with:
MRC p15, 0, <Rd>, c15, c1, 2 ; Read nVAL Reset Enable Set Register
MCR p15, 0, <Rd>, c15, c1, 2 ; Write nVAL Reset Enable Set Register
On reads, this register returns the current setting. On writes, reset requests can be enabled. If a reset request has been enabled, it is disabled by writing to the nVAL Reset Enable Clear Register. See c15, nVAL Reset Enable Clear Register.
If one or more of the reset request fields (P2, P1, P0, and C) is enabled, and the corresponding counter overflows, then a reset request is indicated by nVALRESET being asserted LOW. This signal can be passed to a system reset controller.
The Debug Request Enable Set Register enables any of the PMC Registers, PMC0-PMC2, and CCNT, to generate a debug request on overflow. If enabled, the debug request is signaled by VALEDBGRQ being asserted HIGH.
The nVAL Debug Request Enable Set Register is:
A read/write register.
Always accessible in Privileged mode. The USEREN Register determines access, see c9, User Enable Register.
Figure 4.47 shows the bit arrangement for the nVAL Debug Request Enable Set Register.
Table 4.45 shows how the bit values correspond with the nVAL Debug Request Enable Set Register.
Table 4.45. nVAL Debug Request Enable Set Register bit functions
Bits | Field | Function |
|---|---|---|
| [31] | C | CCNT overflow debug request |
| [30:3] | Reserved | UNP or SBZP |
| [2] | P2 | PMC2 overflow debug request |
| [1] | P1 | PMC1 overflow debug request |
| [0] | P0 | PMC0 overflow debug request |
To access the nVAL Debug Request Enable Set Register, read or write CP15 with:
MRC p15, 0, <Rd>, c15, c1, 3 ; Read nVAL Debug Request Enable Set Register
MCR p15, 0, <Rd>, c15, c1, 3 ; Write nVAL Debug Request Enable Set Register
On reads, this register returns the current setting. On writes, debug requests can be enabled. If a debug request has been enabled, it is disabled by writing to the nVAL Debug Request Enable Clear Register. See c15, nVAL Debug Request Enable Clear Register.
If one or more of the reset request fields (P2, P1, P0, and C) is enabled, and the corresponding counter overflows, then a debug reset request is indicated by VALEDBGRQ being asserted HIGH. This signal can be passed to an external debugger.
The nVAL IRQ Enable Clear Register disables overflow IRQ requests from any of the PMC Registers, PMC0-PMC2, and CCNT, for which they have been enabled.
The nVAL IRQ Enable Clear Register is:
A read/write register.
Always accessible in Privileged mode. The USEREN Register determines access, see c9, User Enable Register.
Figure 4.48 shows the bit arrangement for the nVAL IRQ Enable Clear Register.
Table 4.46 shows how the bit values correspond with the nVAL IRQ Enable Clear Register.
Table 4.46. nVAL IRQ Enable Clear Register bit functions
Bits | Field | Function |
|---|---|---|
| [31] | C | CCNT overflow IRQ request |
| [30:3] | Reserved | UNP or SBZP |
| [2] | P2 | PMC2 overflow IRQ request |
| [1] | P1 | PMC1 overflow IRQ request |
| [0] | P0 | PMC0 overflow IRQ request |
To access the nVAL IRQ Enable Clear Register, read or write CP15 with:
MRC p15, 0, <Rd>, c15, c1, 4 ; Read nVAL IRQ Enable Clear Register
MCR p15, 0, <Rd>, c15, c1, 4 ; Write nVAL IRQ Enable Clear Register
On reads, this register returns the current setting. On writes, overflow interrupt requests that are currently enabled can be disabled.
For more information of how to enable IRQ requests on counter overflows, and how the requests are signaled, see c15, nVAL IRQ Enable Set Register.
The nVAL FIQ Enable Clear Register disables overflow FIQ requests from any of the PMC Registers, PMC0-PMC2, and CCNT, that are enabled.
The nVAL FIQ Enable Clear Register is:
A read/write register.
Always accessible in Privileged mode. The USEREN Register determines access mode, see c9, User Enable Register.
Figure 4.49 shows the bit arrangement for the nVAL FIQ Enable Clear Register.
Table 4.47 shows how the bit values correspond with the FIQ Enable Clear Register.
Table 4.47. nVAL FIQ Enable Clear Register bit functions
Bits | Field | Function |
|---|---|---|
| [31] | C | CCNT overflow FIQ request |
| [30:3] | Reserved | UNP or SBZP |
| [2] | P2 | PMC2 overflow FIQ request |
| [1] | P1 | PMC1 overflow FIQ request |
| [0] | P0 | PMC0 overflow FIQ request |
To access the FIQ Enable Clear Register, read or write CP15 with:
MRC p15, 0, <Rd>, c15, c1, 5 ; Read FIQ Enable Clear Register
MCR p15, 0, <Rd>, c15, c1, 5 ; Write FIQ Enable Clear Register
On reads, this register returns the current setting. On writes, overflow interrupt requests that are currently enabled can be disabled.
For information on how to enable FIQ requests on counter overflows, and how the requests are signaled, see c15, nVAL FIQ Enable Set Register.
The nVAL Reset Enable Clear Register disables overflow reset requests from any of the PMC Registers, PMC0-PMC2, and CCNT, that are enabled.
The nVAL Reset Enable Clear Register is:
A read/write register.
Always accessible in Privileged mode. The USEREN Register determines access, see c9, User Enable Register.
Figure 4.50 shows the bit arrangement for the nVAL Reset Enable Clear Register.
Table 4.48 shows how the bit values correspond with the nVAL Reset Enable Clear Register.
Table 4.48. nVAL Reset Enable Clear Register bit functions
Bits | Field | Function |
|---|---|---|
| [31] | C | CCNT overflow reset request |
| [30:3] | Reserved | UNP or SBZP |
| [2] | P2 | PMC2 overflow reset request |
| [1] | P1 | PMC1 overflow reset request |
| [0] | P0 | PMC0 overflow reset request |
To access the nVAL Reset Enable Clear Register, read or write CP15 with:
MRC p15, 0, <Rd>, c15, c1, 6 ; Read nVAL Reset Enable Clear Register
MCR p15, 0, <Rd>, c15, c1, 6 ; Write nVAL Reset Enable Clear Register
On reads, this register returns the current setting. On writes, overflow reset requests that are currently enabled can be disabled.
For more information of how to enable reset requests on counter overflows, and how the requests are signaled, see c15, nVAL Reset Enable Set Register.
The nVAL Debug Request Enable Clear Register disables overflow debug requests from any of the PMC Registers, PMC0-PMC2, and CCNT, that are enabled.
The nVAL Debug Request Enable Clear Register is:
A read/write register.
Always accessible in Privileged mode. The USEREN Register determines access, see c9, User Enable Register.
Figure 4.51 shows the bit arrangement for the nVAL Debug Request Enable Clear Register.
Table 4.49 shows how the bit values correspond with the nVAL Debug Request Enable Clear Register.
Table 4.49. nVAL Debug Request Enable Clear Register bit functions
Bits | Field | Function |
|---|---|---|
| [31] | C | CCNT overflow debug request |
| [30:3] | Reserved | UNP or SBZP |
| [2] | P2 | PMC2 overflow debug request |
| [1] | P1 | PMC1 overflow debug request |
| [0] | P0 | PMC0 overflow debug request |
To access the nVAL Debug Request Enable Clear Register, read or write CP15 with:
MRC p15, 0, <Rd>, c15, c1, 7 ; Read nVAL Debug Request Enable Clear Register
MCR p15, 0, <Rd>, c15, c1, 7 ; Write nVAL Debug Request Enable Clear Register
On reads, this register returns the current setting. On writes, overflow debug requests that are currently enabled can be disabled.
For more information of how to enable debug requests on counter overflows, and how the requests are signaled, see c15, nVAL Debug Request Enable Set Register.
The nVAL Cache Size Override Register overwrites the caches size fields in the main register. This enables you to choose a smaller instruction and data cache size than is implemented.
The nVAL Cache Size Override Register is:
a write-only register
only accessible in Privileged mode.
Figure 4.52 shows the bit arrangement for the nVAL Cache Size Override Register.
Table 4.50 shows how the bit values correspond with the nVAL Cache Size Override Register.
Table 4.50. nVAL Cache Size Override Register
Bits | Field | Function |
|---|---|---|
| [31:8] | Reserved | SBZ. |
| [7:4] | Dcache | Defines the nVAL data cache size. See Table 4.51. |
| [3:0] | Icache | Defines the nVAL instruction cache size. See Table 4.51. |
Table 4.51 shows the encodings for the nVAL instruction and data cache sizes.
Table 4.51. nVAL instruction and data cache size encodings
| Encoding | Instruction and data cache size |
|---|---|
| b0000 | 4kB |
| b0001 | 8kB |
| b0011 | 16kB |
| b0111 | 32kB |
| b1111 | 64kB |
To access the nVAL Cache Size Override Register, write CP15 with:
MCR p15, 0, <Rd>, c15, c14, 0 ; nVAL Cache Size Override Register
The nVAL Cache Size Override Register can only be used to select cache sizes for which the appropriate RAM has been integrated. Larger cache sizes require deeper data and tag RAMs, and smaller cache sizes require wider tag RAMs. Therefore, it is unlikely that you can change the cache size using this register except using a simulation model of the cache RAMs.
| Copyright © 2009 ARM Limited. All rights reserved. | ARM DDI 0363E |
| Non-Confidential | |
| PDF version | |
| Home > System Control Coprocessor > System control coprocessor registers > Validation Registers |