Cortex-R4 and Cortex-R4F Technical Reference Manual: 4.2.14. c0, Cache Size Selection Register

The Cache Size Selection Register holds the value that the processor uses to select the Current Cache Size Identification Register to use.

The Cache Size Selection Register is:

Figure 4.26 shows the bit arrangement for the Cache Size Selection Register.

Figure 4.26. Cache Size Selection Register format

Table 4.22 shows how the bit values correspond with the Cache Size Selection Register.

Table 4.22. Cache Size Selection Register bit functions

Bits	Field	Function
[31: 4]	Reserved	SBZ.
[3:1]	Level	Identifies which cache level to select. b000 = Level 1 cache This field is read only, writes are ignored.
[0]	InD	Identifies instruction or data cache to use. 1 = instruction 0 = data.

Bits

Field

Function

[31: 4]

Reserved

SBZ.

[3:1]

Level

Identifies which cache level to select.

b000 = Level 1 cache

This field is read only, writes are ignored.

[0]

InD

Identifies instruction or data cache to use.

1 = instruction

0 = data.

To access the Current Cache Size Identification Registers read or write CP15 with:

MRC p15, 2, <Rd>, c0, c0, 0 ; Read Cache Size Selection Register

MCR p15, 2, <Rd>, c0, c0, 0 ; Write Cache Size Selection Register

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