Cortex-R4 and Cortex-R4F Technical Reference Manual: 6.3.2. c9, Count Enable Set Register

6.3.2. c9, Count Enable Set Register

The CouNT ENable Set (CNTENS) Register enables any of the performance monitor count registers. When read, this register indicates which counters are enabled. Writing a 1 to a particular count enable bit enables that counter. Writing a 0 to a count enable bit has no effect. You must use the Count Enable Clear Register to disable the counters.

The CNTENS Register is:

A read/write register.
Always accessible in Privileged mode. The USEREN Register determines accessibility in User mode, see c9, User Enable Register.

The values in this register are ignored unless the E bit, bit [0], is set in the PMNC Register, see c9, Performance Monitor Control Register.

Figure 6.2 shows the bit arrangement for the CNTENS Register.

Figure 6.2. CNTENS Register format

Table 6.3 shows how the bit values correspond with the CNTENS Register.

Table 6.3. CNTENS Register bit functions

Bits	Field	Function
[31]	C	Cycle counter enable set: 0 = disable 1 = enable.
[30:3]	Reserved	UNP on reads, SBZP on writes
[2]	P2	Counter 2 enable
[1]	P1	Counter 1 enable
[0]	P0	Counter 0 enable

To access the CNTENS Register, read or write CP15 with:

MRC p15, 0, <Rd>, c9, c12, 1 ; Read CNTENS Register

MCR p15, 0, <Rd>, c9, c12, 1 ; Write CNTENS Register

The CNTENS Register retains its value when the enable bit of the PMNC is clear, even though its settings are ignored.

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