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Table 1.1 shows the features of the processor that can be configured using either build-configuration or pin-configuration. See Product documentation, design flow, and architecture for information about configuration of the processor. Many of these features, if included, can also be enabled and disabled during software configuration.
Table 1.1. Configurable options
| Feature | Options | Sub-options | Build-configuration or pin-configuration |
|---|---|---|---|
| Redundant core | Single-core (no redundancy) | - | Build |
| Dual-core (redundant) | In-phase clocks Out-of-phase clocks | Build | |
| Instruction cache | No i-cache | - | Build |
| i-cache included | No error checking Parity error checking 64-bit ECC error checking | Build | |
4KB (4x1KB ways) 8KB (4x2KB ways) 16KB (4x4KB ways) 32KB (4x8KB ways) 64KB (4x16KB ways) | Build | ||
| Data cache | No d-cache | - | Build |
| d-cache included | No error checking Parity error checking 32-bit ECC error checking | Build | |
4KB (4x1KB ways) 8KB (4x2KB ways) 16KB (4x4KB ways) 32KB (4x8KB ways) 64KB (4x16KB ways) | Build | ||
| ATCM | No ATCM ports | - | Build and pin |
| One ATCM port | No error checking Parity error checking 32-bit ECC error checking 64-bit ECC error checking | Build | |
| 4KB, 8KB, 16KB, 32KB, 64KB, 128KB, 256KB, 512KB, 1MB, 2MB, 4MB, or 8MB | Pin | ||
| BTCM | No BTCM ports | - | Build and pin |
| One BTCM port (B0TCM) | No error checking Parity error checking 32-bit ECC error checking 64-bit ECC error checking | Build | |
| 4KB, 8KB, 16KB, 32KB, 64KB, 128KB, 256KB, 512KB, 1MB, 2MB, 4MB, or 8MB | Pin | ||
| Two BTCM ports (B0TCM and B1TCM) | No error checking Parity error checking 32-bit ECC error checking 64-bit ECC error checking | Build | |
| 2x2KB, 2x4KB, 2x8KB, 2x16KB, 2x32KB, 2x64KB, 2x128KB, 2x256KB, 2x512KB, 2x1MB, 2x2MB, or 2x4MB | Pin | ||
Interleaved on 64-bit granularity in memory Adjacent in memory | Pin | ||
| Instruction endianness | Little-endian | - | Build |
| Pin-configured | Little-endian Big-endian | Pin | |
| Floating point (VFP) | No FPU | - | Build |
| FPU included[a] | - | ||
| MPU | No MPU | - | Build |
| MPU included | 8 MPU regions 12 MPU regions | Build | |
| TCM bus parity | No TCM address and control bus parity | - | Build |
| TCM address and control bus parity generated | - | ||
| AXI bus parity | No AXI bus parity | - | Build |
| AXI bus parity generated/ checked | - | ||
| Breakpoints | 2-8 breakpoint register pairs | - | Build |
| Watchpoints | 1-8 watchpoint registers | - | Build |
| ATCM at reset | Disabled | - | Pin |
| Enabled[b] | Base address Base address configured | Pin and build | |
| BTCM at reset | Disabled | - | Pin |
| Enabled[b] | Base address configured Base
address | Pin and build | |
| Peripheral ID RevAnd field | Any 4-bit value | - | Build |
| AXI slave interface | No AXI-slave | - | Build |
| AXI-slave included | - | ||
| TCM Hard Error Cache | No TCM Hard Error Cache | - | Build |
| TCM Hard Error Cache included [c] | - | ||
| Non-Maskable FIQ Interrupt | Disabled (FIQ can be masked by software | - | Pin |
| Enabled | - | ||
| Parity type[d] | Odd parity | - | Pin |
| Even parity | - | ||
[a] Only available with the Cortex-R4F processor. [b] Only if the relevant TCM port(s) are included. [c] Only if at least one TCM port is included and uses ECC error checking. [d] Only relevant if at least one TCM port is included and uses parity error checking, one of the caches includes parity checking, or AXI or TCM bus parity is included. | |||
Table 1.2 describes the various features that can be pin-configured to be either enabled or disabled at reset. It also shows which CP15 register field provides software configuration of the feature when the processor is out of reset. All of these fields exist in either the system control register, or one of the auxiliary control registers.
Table 1.2. Configurable options at reset
| Feature | Options | Register |
|---|---|---|
| Exception endianness | Little-endian/big-endian data for exception handling | EE |
| Exception state | ARM/Thumb state for exception handling | TE |
| Exception vector table | Base address for exception vectors: 0x00000000/0xFFFF0000 | V |
| TCM error checking | ATCM parity check enable[a] | ATCMPCEN |
| BTCM parity check enable, for B0TCM and B1TCM independently [a] | B0TCMPCEN/ B1TCMPCEN | |
| ATCM ECC check enable[a] | ATCMPCEN | |
| BTCM ECC check enabled, for B0TCM and B1TCM together[a] | B0TCMPCEN/ B1TCMPCEN | |
| TCM external errors | ATCM external error enable | ATCMECEN |
| BTCM external error enable, for B0TCM and B1TCM independently | B0TCMECEN/ B1TCMECEN | |
| TCM load/store-64 (read-modify-write) behavior | ATCM load/store-64 enable[b] | ATCMRMW |
| BTCM load/store-64 enable[b] | BTCMRMW | |
[a] Can only be enabled if the appropriate TCM is configured with the appropriate error checking scheme, and the appropriate number of ports [b] Can only be enabled if the appropriate TCM is not configured with 32-bit ECC. | ||
| Copyright © 2009 ARM Limited. All rights reserved. | ARM DDI 0363E |
| Non-Confidential | |
| PDF version | |
| Home > Introduction > Configurable options |