| Copyright © 2009 ARM Limited. All rights reserved. | ARM DDI 0363E |
| Non-Confidential | |
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| Home > Level Two Interface > AXI master interface > Linefill buffers and the AXI master interface |
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On the data side there are two LineFill Buffers (LFBs), LFB0 and LFB1. Each request from the data cache controller or from the STore Buffer (STB) can be allocated to either LFB0 or LFB1.
On the instruction side, there is one LFB. This is the Instruction LFB (ILFB), that treats instruction linefill requests or Non-cacheable instruction reads in the same way.
The linefill buffers:
get returned data from the AXI bus for linefill requests
get returned data from the AXI bus for any Non-cacheable LDR or LDMs
get data from the STB to write as a burst on the AXI bus (LFB0 and LFB1 only).
Single writes do not use LFBs.
The LFBs are 256 bits wide so that an entire cache line can be written to the cache RAMs in one cycle. While the LFB is being filled from L2 memory, its bytes can be merged with write data from the STB.
| Copyright © 2009 ARM Limited. All rights reserved. | ARM DDI 0363E |
| Non-Confidential | |
| PDF version | |
| Home > Level Two Interface > AXI master interface > Linefill buffers and the AXI master interface |