Cortex-R4 and Cortex-R4F Technical Reference Manual: 7.1. About the MPU

7.1. About the MPU

The MPU works with the L1 memory system to control accesses to and from L1 and external memory. For a full architectural description of the MPU, see the ARM Architecture Reference Manual.

The MPU enables you to partition memory into regions and set individual protection attributes for each region. The MPU supports zero, eight, or twelve memory regions.

Note

If the MPU has zero regions, you cannot enable or program the MPU. Attributes are only determined from the default memory map when zero regions are implemented.

Each region is programmed with a base address and size, and the regions can be overlapped to enable efficient programming of the memory map. To support overlapping, the regions are assigned priorities, with region 0 having the lowest priority and region 11 having the highest. The MPU returns access permissions and attributes for the highest priority region where the address hits.

The MPU is programmed using CP15 registers c1 and c6, see MPU control and configuration. Memory region control read and write access is permitted only from Privileged modes.

Table 7.1 shows the default memory map.

Table 7.1. Default memory map

Address range	Instruction memory type		Data memory type		Execute Never
Address range	Instruction cache enabled	Instruction cache disabled	Data cache enabled	Data cache disabled	Execute Never
`0xFFFFFFFF`	Normal Non-cacheable only if HIVECS is TRUE	Normal Non-cacheable only if HIVECS is TRUE	Strongly Ordered	Strongly Ordered	Instruction execution only permitted if HIVECS is TRUE
`0xF0000000`	Normal Non-cacheable only if HIVECS is TRUE	Normal Non-cacheable only if HIVECS is TRUE	Strongly Ordered	Strongly Ordered	Instruction execution only permitted if HIVECS is TRUE
`0xEFFFFFFF`	-	-	Strongly Ordered	Strongly Ordered	Execute Never
`0xC0000000`	-	-	Strongly Ordered	Strongly Ordered	Execute Never
`0xBFFFFFFF`	-	-	Shared Device	Shared Device	Execute Never
`0xA0000000`	-	-	Shared Device	Shared Device	Execute Never
`0x9FFFFFFF`	-	-	Non-shared Device	Non-shared Device	Execute Never
`0x80000000`	-	-	Non-shared Device	Non-shared Device	Execute Never
`0x7FFFFFFF`	Normal, Cacheable, Non-shared	Normal, Non-cacheable, Non-shared	Normal, Non-cacheable, Shared	Normal, Non-cacheable, Shared	Instruction execution permitted
`0x60000000`	Normal, Cacheable, Non-shared	Normal, Non-cacheable, Non-shared	Normal, Non-cacheable, Shared	Normal, Non-cacheable, Shared	Instruction execution permitted
`0x5FFFFFF`	Normal, Cacheable, Non-shared	Normal, Non-cacheable, Non-shared	Normal, WT Cacheable, Non-shared	Normal, Non-cacheable, Shared	Instruction execution permitted
`0x40000000`	Normal, Cacheable, Non-shared	Normal, Non-cacheable, Non-shared	Normal, WT Cacheable, Non-shared	Normal, Non-cacheable, Shared	Instruction execution permitted
`0x3FFFFFFF`	Normal, Cacheable, Non-shared	Normal, Non-cacheable, Non-shared	Normal, WBWA Cacheable, Non-shared	Normal, Non-cacheable, Shared	Instruction execution permitted
`0x00000000`	Normal, Cacheable, Non-shared	Normal, Non-cacheable, Non-shared	Normal, WBWA Cacheable, Non-shared	Normal, Non-cacheable, Shared	Instruction execution permitted

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