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The processor contains one CPSR and five SPSRs for exception handlers to use. The program status registers:
hold information about the most recently performed ALU operation
control the enabling and disabling of interrupts
set the processor operating mode.
Figure 2.4 shows the bit arrangement in the status registers.
The following sections explain the meanings of these bits:
| Copyright © 2009 ARM Limited. All rights reserved. | ARM DDI 0363E |
| Non-Confidential | |
| PDF version | |
| Home > Programmer’s Model > Program status registers |