Cortex™-R4 and Cortex-R4F Technical Reference Manual

Revision: r1p3


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Conventions
Further reading
Feedback
Feedback on this product
Feedback on this book
1. Introduction
1.1. About the processor
1.2. About the architecture
1.3. Components of the processor
1.3.1. Data Processing Unit
1.3.2. Load/store unit
1.3.3. Prefetch unit
1.3.4. L1 memory system
1.3.5. L2 AXI interfaces
1.3.6. Debug
1.3.7. System control coprocessor
1.3.8. Interrupt handling
1.4. External interfaces of the processor
1.4.1. APB Debug interface
1.4.2. ETM interface
1.4.3. Test interface
1.5. Power management
1.6. Configurable options
1.7. Execution pipeline stages
1.8. Redundant core comparison
1.9. Test features
1.10. Product documentation, design flow, and architecture
1.10.1. Documentation
1.10.2. Design flow
1.10.3. Architectural information
1.11. Product revision information
1.11.1. Processor identification
1.11.2. Architectural information
2. Programmer’s Model
2.1. About the programmer’s model
2.2. Instruction set states
2.2.1. Switching state
2.2.2. Interworking ARM and Thumb state
2.3. Operating modes
2.4. Data types
2.5. Memory formats
2.5.1. Byte-invariant big-endian format
2.5.2. Little-endian format
2.6. Registers
2.6.1. The register set
2.7. Program status registers
2.7.1. The N, Z, C, and V bits
2.7.2. The Q bit
2.7.3. The IT bits
2.7.4. The J bit
2.7.5. The DNM bits
2.7.6. The GE bits
2.7.7. The E bit
2.7.8. The A bit
2.7.9. The I and F bits
2.7.10. The T bit
2.7.11. The M bits
2.7.12. Modification of PSR bits by MSR instructions
2.8. Exceptions
2.8.1. Exception entry and exit summary
2.8.2. Reset
2.8.3. Interrupts
2.8.4. Aborts
2.8.5. Supervisor call instruction
2.8.6. Undefined instruction
2.8.7. Breakpoint instruction
2.8.8. Exception vectors
2.9. Acceleration of execution environments
2.10. Unaligned and mixed-endian data access support
2.11. Big-endian instruction support
3. Processor Initialization, Resets, and Clocking
3.1. Initialization
3.1.1. MPU
3.1.2. CRS
3.1.3. FPU
3.1.4. Caches
3.1.5. TCM
3.2. Resets
3.3. Reset modes
3.3.1. Power-on reset
3.3.2. Processor reset
3.3.3. Normal operation
3.3.4. Halt operation
3.4. Clocking
3.4.1. AXI interface clocking
3.4.2. Clock gating
4. System Control Coprocessor
4.1. About the system control coprocessor
4.1.1. System control coprocessor functional groups
4.1.2. System control and configuration
4.1.3. MPU control and configuration
4.1.4. Cache control and configuration
4.1.5. TCM control and configuration
4.1.6. System performance monitor
4.1.7. System validation
4.2. System control coprocessor registers
4.2.1. Register allocation
4.2.2. c0, Main ID Register
4.2.3. c0, Cache Type Register
4.2.4. c0, TCM Type Register
4.2.5. c0, MPU Type Register
4.2.6. c0, Multiprocessor ID Register
4.2.7. The Processor Feature Registers
4.2.8. c0, Debug Feature Register 0
4.2.9. c0, Auxiliary Feature Register 0
4.2.10. Memory Model Feature Registers
4.2.11. Instruction Set Attributes Registers
4.2.12. c0, Current Cache Size Identification Register
4.2.13. c0, Current Cache Level ID Register
4.2.14. c0, Cache Size Selection Register
4.2.15. c1, System Control Register
4.2.16. Auxiliary Control Registers
4.2.17. c1, Coprocessor Access Register
4.2.18. Fault Status and Address Registers
4.2.19. c6, MPU memory region programming registers
4.2.20. Cache operations
4.2.21. c9, BTCM Region Register
4.2.22. c9, ATCM Region Register
4.2.23. c9, TCM Selection Register
4.2.24. c11, Slave Port Control Register
4.2.25. c13, FCSE PID Register
4.2.26. c13, Context ID Register
4.2.27. c13, Thread and Process ID Registers
4.2.28. Validation Registers
4.2.29. Correctable Fault Location Register
4.2.30. Build Options Registers
5. Prefetch Unit
5.1. About the prefetch unit
5.2. Branch prediction
5.2.1. Disabling program flow prediction
5.2.2. Branch predictor
5.2.3. Incorrect predictions and correction
5.3. Return stack
6. Events and Performance Monitor
6.1. About the events
6.2. About the PMU
6.3. Performance monitoring registers
6.3.1. c9, Performance Monitor Control Register
6.3.2. c9, Count Enable Set Register
6.3.3. c9, Count Enable Clear Register
6.3.4. c9, Overflow Flag Status Register
6.3.5. c9, Software Increment Register
6.3.6. c9, Performance Counter Selection Register
6.3.7. c9, Cycle Count Register
6.3.8. c9, Event Selection Register
6.3.9. c9, Performance Monitor Count Registers
6.3.10. c9, User Enable Register
6.3.11. c9, Interrupt Enable Set Register
6.3.12. c9, Interrupt Enable Clear Register
6.4. Event bus interface
6.4.1. Use of the event bus and counters
7. Memory Protection Unit
7.1. About the MPU
7.1.1. Memory regions
7.1.2. Overlapping regions
7.1.3. Background regions
7.1.4. TCM regions
7.2. Memory types
7.2.1. Using memory types
7.3. Region attributes
7.3.1. Cacheable memory policies
7.4. MPU interaction with memory system
7.5. MPU faults
7.5.1. Background fault
7.5.2. Permission fault
7.5.3. Alignment fault
7.6. MPU software-accessible registers
8. Level One Memory System
8.1. About the L1 memory system
8.2. About the error detection and correction schemes
8.2.1. Parity
8.2.2. Error checking and correction
8.2.3. Read-Modify-Write
8.2.4. Hard errors
8.2.5. Error correction
8.3. Fault handling
8.3.1. Faults
8.3.2. Fault status information
8.3.3. Correctable Fault Location Register
8.3.4. Usage models
8.4. About the TCMs
8.4.1. TCM attributes and permissions
8.4.2. ATCM and BTCM configuration
8.4.3. TCM internal error detection and correction
8.4.4. TCM arbitration
8.4.5. TCM initialization
8.4.6. TCM port protocol
8.4.7. External TCM errors
8.4.8. AXI slave interfaces for TCMs
8.5. About the caches
8.5.1. Store buffer
8.5.2. Cache maintenance operations
8.5.3. Cache error detection and correction
8.5.4. Cache RAM organization
8.5.5. Cache interaction with memory system
8.6. Internal exclusive monitor
8.7. Memory types and L1 memory system behavior
8.8. Error detection events
8.8.1. TCM error events
8.8.2. Instruction-cache error events
8.8.3. Data-cache error events
8.8.4. Events and the CFLR
9. Level Two Interface
9.1. About the L2 interface
9.2. AXI master interface
9.2.1. Identifiers for AXI bus accesses
9.2.2. Write response
9.2.3. Linefill buffers and the AXI master interface
9.2.4. Eviction buffer
9.2.5. Memory attributes
9.3. AXI master interface transfers
9.3.1. Restrictions on AXI transfers
9.3.2. Strongly Ordered and Device transactions
9.3.3. Linefills
9.3.4. Cache line write-back (eviction)
9.3.5. Non-cacheable reads
9.3.6. Non-cacheable or write-through writes
9.3.7. AXI transaction splitting
9.3.8. Normal write merging
9.4. AXI slave interface
9.4.1. AXI slave interface for cache RAMs
9.4.2. TCM parity and ECC support
9.4.3. External TCM errors
9.4.4. Cache parity and ECC support
9.4.5. AXI slave control
9.4.6. AXI slave characteristics
9.5. Enabling or disabling AXI slave accesses
9.6. Accessing RAMs using the AXI slave interface
9.6.1. TCM RAM access
9.6.2. Cache RAM access
10. Power Control
10.1. About power control
10.2. Power management
10.2.1. Run mode
10.2.2. Standby mode
10.2.3. Dormant mode
10.2.4. Shutdown mode
10.2.5. Communication to the Power Management Controller
11. Debug
11.1. Debug systems
11.1.1. Debug host
11.1.2. Protocol converter
11.1.3. Debug target
11.2. About the debug unit
11.2.1. Halting debug-mode debugging
11.2.2. Monitor debug-mode debugging
11.2.3. Programming the debug unit
11.3. Debug register interface
11.3.1. Coprocessor registers
11.3.2. CP14 access permissions
11.3.3. Coprocessor registers summary
11.3.4. Memory-mapped registers
11.3.5. Memory addresses for breakpoints and watchpoints
11.3.6. Power domains
11.3.7. Effects of resets on debug registers
11.3.8. APB port access permissions
11.4. Debug register descriptions
11.4.1. Accessing debug registers
11.4.2. CP14 c0, Debug ID Register
11.4.3. CP14 c0, Debug ROM Address Register
11.4.4. CP14 c0, Debug Self Address Offset Register
11.4.5. CP14 c1, Debug Status and Control Register
11.4.6. Data Transfer Register
11.4.7. Watchpoint Fault Address Register
11.4.8. Vector Catch Register
11.4.9. Debug State Cache Control Register
11.4.10. Instruction Transfer Register
11.4.11. Debug Run Control Register
11.4.12. Breakpoint Value Registers
11.4.13. Breakpoint Control Registers
11.4.14. Watchpoint Value Registers
11.4.15. Watchpoint Control Registers
11.4.16. Operating System Lock Status Register
11.4.17. Authentication Status Register
11.4.18. Device Power-down and Reset Control Register
11.4.19. Device Power-down and Reset Status Register
11.5. Management registers
11.5.1. Processor ID Registers
11.5.2. Claim Registers
11.5.3. Lock Access Register
11.5.4. Lock Status Register
11.5.5. Device Type Register
11.5.6. Debug Identification Registers
11.6. Debug events
11.6.1. Software debug event
11.6.2. Halting debug event
11.6.3. Behavior of the processor on debug events
11.6.4. Debug event priority
11.6.5. Watchpoint debug events
11.7. Debug exception
11.7.1. Effect of debug exceptions on CP15 registers and WFAR
11.7.2. Avoiding unrecoverable states
11.8. Debug state
11.8.1. Entering debug state
11.8.2. Behavior of the PC and CPSR in debug state
11.8.3. Executing instructions in debug state
11.8.4. Writing to the CPSR in debug state
11.8.5. Privilege
11.8.6. Accessing registers and memory
11.8.7. Coprocessor instructions
11.8.8. Effect of debug state on non-invasive debug
11.8.9. Effects of debug events on processor registers
11.8.10. Exceptions in debug state
11.8.11. Leaving debug state
11.9. Cache debug
11.9.1. Cache pollution in debug state
11.9.2. Cache coherency in debug state
11.9.3. Cache usage profiling
11.10. External debug interface
11.10.1. APB signals
11.10.2. Miscellaneous debug signals
11.10.3. Authentication signals
11.11. Using the debug functionality
11.11.1. Debug communications channel
11.11.2. Programming breakpoints and watchpoints
11.11.3. Single-stepping
11.11.4. Debug state entry
11.11.5. Debug state exit
11.11.6. Accessing registers and memory in debug state
11.12. Debugging systems with energy management capabilities
11.12.1. Emulating power down
12. FPU Programmer’s Model
12.1. About the FPU programmer’s model
12.1.1. FPU functionality
12.1.2. About the VFPv3-D16 architecture
12.2. General-purpose registers
12.2.1. FPU views of the register bank
12.3. System registers
12.3.1. Floating-Point System ID Register, FPSID
12.3.2. Floating-Point Status and Control Register, FPSCR
12.3.3. Floating-Point Exception Register, FPEXC
12.3.4. Media and VFP Feature Registers, MVFR0 and MVFR1
12.4. Modes of operation
12.4.1. Full-compliance mode
12.4.2. Flush-to-zero mode
12.4.3. Default NaN mode
12.5. Compliance with the IEEE 754 standard
12.5.1. Complete implementation of the IEEE 754 standard
12.5.2. IEEE 754 standard implementation choices
12.5.3. Exceptions
13. Integration Test Registers
13.1. About Integration Test Registers
13.2. Programming and reading Integration Test Registers
13.2.1. Software access using APB
13.3. Summary of the processor registers used for integration testing
13.4. Processor integration testing
13.4.1. Using the Integration Test Registers
13.4.2. Performing integration testing
13.4.3. ITETMIF Register (ETM interface)
13.4.4. ITMISCOUT Register (Miscellaneous Outputs)
13.4.5. ITMISCIN Register (Miscellaneous Inputs)
13.4.6. Integration Mode Control Register (ITCTRL)
14. Cycle Timings and Interlock Behavior
14.1. About cycle timings and interlock behavior
14.1.1. Instruction execution overview
14.1.2. Conditional instructions
14.1.3. Flag-setting instructions
14.1.4. Definition of terms
14.1.5. Assembler language syntax
14.2. Register interlock examples
14.3. Data processing instructions
14.3.1. Cycle counts if destination is not PC
14.3.2. Cycle counts if destination is the PC
14.3.3. Example interlocks
14.4. QADD, QDADD, QSUB, and QDSUB instructions
14.5. Media data-processing
14.6. Sum of Absolute Differences (SAD)
14.6.1. Example interlocks
14.7. Multiplies
14.8. Divide
14.9. Branches
14.10. Processor state updating instructions
14.11. Single load and store instructions
14.11.1. Base register update
14.12. Load and Store Double instructions
14.13. Load and Store Multiple instructions
14.13.1. Load and Store Multiples, other than load multiples including the PC
14.13.2. Load Multiples, where the PC is in the register list
14.13.3. Example Interlocks
14.14. RFE and SRS instructions
14.15. Synchronization instructions
14.16. Coprocessor instructions
14.17. SVC, BKPT, Undefined, and Prefetch Aborted instructions
14.18. Miscellaneous instructions
14.19. Floating-point register transfer instructions
14.20. Floating-point load/store instructions
14.21. Floating-point single-precision data processing instructions
14.22. Floating-point double-precision data processing instructions
14.23. Dual issue
14.23.1. Dual issue rules
14.23.2. Permitted combinations
15. AC Characteristics
15.1. Processor timing
15.2. Processor timing parameters
15.2.1. Input port timing parameters
15.2.2. Output ports timing parameters
A. Processor Signal Descriptions
A.1. About the processor signal descriptions
A.2. Global signals
A.3. Configuration signals
A.4. Interrupt signals, including VIC interface signals
A.5. L2 interface signals
A.5.1. AXI master port
A.5.2. AXI master port error detection signals
A.5.3. AXI slave port
A.5.4. AXI slave port error detection signals
A.6. TCM interface signals
A.7. Dual core interface signals
A.8. Debug interface signals
A.9. ETM interface signals
A.10. Test signals
A.11. MBIST signals
A.12. Validation signals
A.13. FPU signals
B. ECC Schemes
B.1. ECC scheme selection guidelines
C. Revisions
Glossary

List of Figures

1. Key to timing diagram conventions
1.1. Processor block diagram
1.2. Processor Fetch and Decode pipeline stages
1.3. Cortex-R4 Issue and Execution pipeline stages
1.4. Cortex-R4F Issue and Execution pipeline stages
2.1. Byte-invariant big-endian (BE-8) format
2.2. Little-endian format
2.3. Register organization
2.4. Program status register
2.5. Interrupt entry sequence
3.1. Power-on reset
3.2. AXI interface clocking
4.1. System control and configuration registers
4.2. MPU control and configuration registers
4.3. Cache control and configuration registers
4.4. TCM control and configuration registers
4.5. System performance monitor registers
4.6. System validation registers
4.7. Main ID Register format
4.8. Cache Type Register format
4.9. TCM Type Register format
4.10. MPU Type Register format
4.11. Multiprocessor ID Register format
4.12. Processor Feature Register 0 format
4.13. Processor Feature Register 1 format
4.14. Debug Feature Register 0 format
4.15. Memory Model Feature Register 0 format
4.16. Memory Model Feature Register 1 format
4.17. Memory Model Feature Register 2 format
4.18. Memory Model Feature Register 3 format
4.19. Instruction Set Attributes Register 0 format
4.20. Instruction Set Attributes Register 1 format
4.21. Instruction Set Attributes Register 2 format
4.22. Instruction Set Attributes Register 3 format
4.23. Instruction Set Attributes Register 4 format
4.24. Current Cache Size Identification Register format
4.25. Current Cache Level ID Register format
4.26. Cache Size Selection Register format
4.27. System Control Register format
4.28. Auxiliary Control Register format
4.29. Secondary Auxiliary Control Register format
4.30. Coprocessor Access Register format
4.31. Data Fault Status Register format
4.32. Instruction Fault Status Register format
4.33. Auxiliary fault status registers format
4.34. MPU Region Base Address Registers format
4.35. MPU Region Size and Enable Registers format
4.36. MPU Region Access Control Register format
4.37. MPU Memory Region Number Register format
4.38. Cache operations
4.39. c7 format for Set and Way
4.40. Cache operations address format
4.41. BTCM Region Registers
4.42. ATCM Region Registers
4.43. Slave Port Control Register
4.44. nVAL IRQ Enable Set Register format
4.45. nVAL FIQ Enable Set Register format
4.46. nVAL Reset Enable Set Register format
4.47. nVAL Debug Request Enable Set Register format
4.48. nVAL IRQ Enable Clear Register format
4.49. nVAL FIQ Enable Clear Register format
4.50. nVAL Reset Enable Clear Register format
4.51. nVAL Debug Request Enable Clear Register format
4.52. nVAL Cache Size Override Register format
4.53. Correctable Fault Location Register - cache
4.54. Correctable Fault Location Register - TCM
4.55. Build Options 1 Register format
4.56. Build Options 2 Register format
6.1. PMNC Register format
6.2. CNTENS Register format
6.3. CNTENC Register format
6.4. FLAG Register format
6.5. SWINCR Register format
6.6. PMNXSEL Register format
6.7. EVTSELx Register format
6.8. USEREN Register format
6.9. INTENS Register format
6.10. INTENC Register format
7.1. Overlapping memory regions
7.2. Overlay for stack protection
7.3. Overlapping subregion of memory
8.1. L1 memory system block diagram
8.2. Error detection and correction schemes
8.3. Nonsequential read operation performed with one RAM access.
8.4. Sequential read operation performed with one RAM access
11.1. Typical debug system
11.2. Debug ID Register format
11.3. Debug ROM Address Register format
11.4. Debug Self Address Offset Register format
11.5. Debug Status and Control Register format
11.6. Watchpoint Fault Address Register format
11.7. Vector Catch Register format
11.8. Debug State Cache Control Register format
11.9. Debug Run Control Register format
11.10. Breakpoint Control Registers format
11.11. Watchpoint Control Registers format
11.12. OS Lock Status Register format
11.13. Authentication Status Register format
11.14. PRCR format
11.15. PRSR format
11.16. Claim Tag Set Register format
11.17. Claim Tag Clear Register format
11.18. Lock Status Register format
11.19. Device Type Register format
12.1. FPU register bank
12.2. Floating-Point System ID Register format
12.3. Floating-Point Status and Control Register format
12.4. Floating-Point Exception Register format
12.5. MVFR0 Register format
12.6. MVFR1 Register format
13.1. ITETMIF Register bit assignments
13.2. ITMISCOUT Register bit assignments
13.3. ITMISCIN Register bit assignments
13.4. ITCTRL Register bit assignments

List of Tables

1.1. Configurable options
1.2. Configurable options at reset
1.3. ID values for different product versions
2.1. Register mode identifiers
2.2. GE[3:0] settings
2.3. PSR mode bit values
2.4. Exception entry and exit
2.5. Configuration of exception vector address locations
2.6. Exception vectors
2.7. Jazelle register instruction summary
3.1. Reset modes
4.1. System control coprocessor register functions
4.2. Summary of CP15 registers and operations
4.3. Main ID Register bit functions
4.4. Cache Type Register bit functions
4.5. TCM Type Register bit functions
4.6. MPU Type Register bit functions
4.7. Processor Feature Register 0 bit functions
4.8. Processor Feature Register 1 bit functions
4.9. Debug Feature Register 0 bit functions
4.10. Memory Model Feature Register 0 bit functions
4.11. Memory Model Feature Register 1 bit functions
4.12. Memory Model Feature Register 2 bit functions
4.13. Memory Model Feature Register 3 bit functions
4.14. Instruction Set Attributes Register 0 bit functions
4.15. Instruction Set Attributes Register 1 bit functions
4.16. Instruction Set Attributes Register 2 bit functions
4.17. Instruction Set Attributes Register 3 bit functions
4.18. Instruction Set Attributes Register 4 bit functions
4.19. Current Cache Size Identification Register bit functions
4.20. Bit field and register encodings for Current Cache Size Identification Register
4.21. Current Cache Level ID Register bit functions
4.22. Cache Size Selection Register bit functions
4.23. System Control Register bit functions
4.24. Auxiliary Control Register bit functions
4.25. Secondary Auxiliary Control Register bit functions
4.26. Coprocessor Access Register bit functions
4.27. Fault Status Register encodings
4.28. Data Fault Status Register bit functions
4.29. Instruction Fault Status Register bit functions
4.30. ADFSR and AIFSR bit functions
4.31. MPU Region Base Address Registers bit functions
4.32. Region Size Register bit functions
4.33. MPU Region Access Control Register bit functions
4.34. Access data permission bit encoding
4.35. MPU Memory Region Number Register bit functions
4.36. Functional bits of c7 for Set and Way
4.37. Widths of the set field for L1 cache sizes
4.38. Functional bits of c7 for address format
4.39. BTCM Region Register bit functions
4.40. ATCM Region Register bit functions
4.41. Slave Port Control Register bit functions
4.42. nVAL IRQ Enable Set Register bit functions
4.43. nVAL FIQ Enable Set Register bit functions
4.44. nVAL Reset Enable Set Register bit functions
4.45. nVAL Debug Request Enable Set Register bit functions
4.46. nVAL IRQ Enable Clear Register bit functions
4.47. nVAL FIQ Enable Clear Register bit functions
4.48. nVAL Reset Enable Clear Register bit functions
4.49. nVAL Debug Request Enable Clear Register bit functions
4.50. nVAL Cache Size Override Register
4.51. nVAL instruction and data cache size encodings
4.52. Correctable Fault Location Register - cache
4.53. Correctable Fault Location Register - TCM
4.54. Build Options 1 Register
4.55. Build Options 2 Register
6.1. Event bus interface bit functions
6.2. PMNC Register bit functions
6.3. CNTENS Register bit functions
6.4. CNTENC Register bit functions
6.5. Overflow Flag Status Register bit functions
6.6. SWINCR Register bit functions
6.7. Performance Counter Selection Register bit functions
6.8. EVTSELx Register bit functions
6.9. USEREN Register bit functions
6.10. INTENS Register bit functions
6.11. INTENC Register bit functions
7.1. Default memory map
7.2. Memory attributes summary
7.3. TEX[2:0], C, and B encodings
7.4. Inner and Outer cache policy encoding
8.1. Types of aborts
8.2. Cache parity error behavior
8.3. Cache ECC error behavior
8.4. Tag RAM bit descriptions, with parity
8.5. Tag RAM bit descriptions, with ECC
8.6. Tag RAM bit descriptions, no parity or ECC
8.7. Cache sizes and tag RAM organization
8.8. Organization of a dirty RAM line
8.9. Instruction cache data RAM sizes, no parity or ECC
8.10. Data cache data RAM sizes, no parity or ECC
8.11. Instruction cache data RAM sizes, with parity
8.12. Data cache data RAM sizes, with parity
8.13. Data cache RAM bits, with parity
8.14. Instruction cache data RAM sizes with ECC
8.15. Data cache data RAM sizes with ECC
8.16. Data cache RAM bits, with ECC
8.17. Memory types and associated behavior
9.1. AXI master interface attributes
9.2. ARCACHEM and AWCACHEM encodings
9.3. ARUSERM and AWUSERM encodings
9.4. Non-cacheable LDRB
9.5. LDRH from Strongly Ordered or Device memory
9.6. LDR or LDM1 from Strongly Ordered or Device memory
9.7. LDM5, Strongly Ordered or Device memory
9.8. STRB to Strongly Ordered or Device memory
9.9. STRH to Strongly Ordered or Device memory
9.10. STR or STM1 to Strongly Ordered or Device memory
9.11. STM7 to Strongly Ordered or Device memory to word 0 or 1
9.12. Linefill behavior on the AXI interface
9.13. Cache line write-back
9.14. LDRH from Non-cacheable Normal memory
9.15. LDR or LDM1 from Non-cacheable Normal memory
9.16. LDM5, Non-cacheable Normal memory or cache disabled
9.17. STRH to Cacheable write-through or Non-cacheable Normal memory
9.18. STR or STM1 to Cacheable write-through or Non-cacheable Normal memory
9.19. AXI transaction splitting, all six words in same cache line
9.20. AXI transaction splitting, data in two cache lines
9.21. Non-cacheable LDR or LDM1 crossing a cache line boundary
9.22. Cacheable write-through or Non-cacheable STRH crossing a cache line boundary
9.23. AXI transactions for Strongly Ordered or Device type memory
9.24. AXI transactions for Non-cacheable Normal or Cacheable write-through memory
9.25. AXI slave interface attributes
9.26. RAM region decode
9.27. TCM chip-select decode
9.28. MSB bit for the different TCM RAM sizes
9.29. Cache RAM chip-select decode
9.30. Cache tag/valid RAM bank/address decode
9.31. Cache data RAM bank/address decode
9.32. Data format, instruction cache and data cache, no parity and no ECC
9.33. Data format, instruction cache and data cache, with parity
9.34. Data format, instruction cache, with ECC
9.35. Data format, data cache, with ECC
9.36. Tag register format for reads, no parity or ECC
9.37. Tag register format for reads, with parity
9.38. Tag register format for reads, with ECC
9.39. Tag register format for writes, no parity or ECC
9.40. Tag register format for writes, with parity
9.41. Tag register format for writes, with ECC
9.42. Dirty register format, with parity or with no error scheme
9.43. Dirty register format, with ECC
11.1. Access to CP14 debug registers
11.2. CP14 debug registers summary
11.3. Debug memory-mapped registers
11.4. External debug interface access permissions
11.5. Terms used in register descriptions
11.6. CP14 debug register map
11.7. Debug ID Register functions
11.8. Debug ROM Address Register functions
11.9. Debug Self Address Offset Register functions
11.10. Debug Status and Control Register functions
11.11. Data Transfer Register functions
11.12. Watchpoint Fault Address Register functions
11.13. Vector Catch Register functions
11.14. Debug State Cache Control Register functions
11.15. Debug Run Control Register functions
11.16. Breakpoint Value Registers functions
11.17. Breakpoint Control Registers functions
11.18. Meaning of BVR bits [22:20]
11.19. Watchpoint Value Registers functions
11.20. Watchpoint Control Registers functions
11.21. OS Lock Status Register functions
11.22. Authentication Status Register bit functions
11.23. PRCR functions
11.24. PRSR functions
11.25. Management Registers
11.26. Processor Identifier Registers
11.27. Claim Tag Set Register functions
11.28. Functional bits of the Claim Tag Clear Register
11.29. Lock Status Register functions
11.30. Device Type Register functions
11.31. Peripheral Identification Registers
11.32. Fields in the Peripheral Identification Registers
11.33. Peripheral ID Register 0 functions
11.34. Peripheral ID Register 1 functions
11.35. Peripheral ID Register 2 functions
11.36. Peripheral ID Register 3 functions
11.37. Peripheral ID Register 4 functions
11.38. Component Identification Registers
11.39. Processor behavior on debug events
11.40. Values in link register after exceptions
11.41. Read PC value after debug state entry
11.42. Authentication signal restrictions
11.43. Values to write to BCR for a simple breakpoint
11.44. Values to write to WCR for a simple watchpoint
11.45. Example byte address masks for watchpointed objects
12.1. VFP system registers
12.2. Accessing VFP system registers
12.3. FPSID Register bit functions
12.4. FPSCR Register bit functions
12.5. Floating-Point Exception Register bit functions
12.6. MVFR0 Register bit functions
12.7. MVFR1 Register bit functions
12.8. Default NaN values
12.9. QNaN and SNaN handling
13.1. Integration Test Registers summary
13.2. Output signals that can be controlled by the Integration Test Registers
13.3. Input signals that can be read by the Integration Test Registers
13.4. ITETMIF Register bit assignments
13.5. ITMISCOUT Register bit assignments
13.6. ITMISCIN Register bit assignments
13.7. ITCTRL Register bit assignments
14.1. Definition of cycle timing terms
14.2. Register interlock examples
14.3. Data Processing Instruction cycle timing behavior if destination is not PC
14.4. Data Processing instruction cycle timing behavior if destination is the PC
14.5. QADD, QDADD, QSUB, and QDSUB instruction cycle timing behavior
14.6. Media data-processing instructions cycle timing behavior
14.7. Sum of absolute differences instruction timing behavior
14.8. Example interlocks
14.9. Example multiply instruction cycle timing behavior
14.10. Branch instruction cycle timing behavior
14.11. Processor state updating instructions cycle timing behavior
14.12. Cycle timing behavior for stores and loads, other than loads to the PC
14.13. Cycle timing behavior for loads to the PC
14.14. <addr_md_1cycle> and <addr_md_3cycle> LDR example instruction explanation
14.15. Load and Store Double instructions cycle timing behavior
14.16. <addr_md_1cycle> and <addr_md_3cycle> LDRD example instruction explanation
14.17. Cycle timing behavior of Load and Store Multiples, other than load multiples including the PC
14.18. Cycle timing behavior of Load Multiples, with PC in the register list (64-bit aligned)
14.19. RFE and SRS instructions cycle timing behavior
14.20. Synchronization instructions cycle timing behavior
14.21. Coprocessor instructions cycle timing behavior
14.22. SVC, BKPT, Undefined, prefetch aborted instructions cycle timing behavior
14.23. IT and NOP instructions cycle timing behavior
14.24. Floating-point register transfer instructions cycle timing behavior
14.25. Floating-point load/store instructions cycle timing behavior
14.26. Floating-point single-precision data processing instructions cycle timing behavior
14.27. Floating-point double-precision data processing instructions cycle timing behavior
14.28. Permitted instruction combinations
15.1. Miscellaneous input ports timing parameters:
15.2. Configuration input port timing parameters
15.3. Interrupt input ports timing parameters
15.4. AXI master input port timing parameters
15.5. AXI slave input port timing parameters
15.6. Debug input ports timing parameters
15.7. ETM input ports timing parameters
15.8. Test input ports timing parameters
15.9. TCM interface input ports timing parameters
15.10. Miscellaneous output port timing parameter
15.11. Interrupt output ports timing parameters
15.12. AXI master output port timing parameters
15.13. AXI slave output ports timing parameters
15.14. Debug interface output ports timing parameters
15.15. ETM interface output ports timing parameters
15.16. Test output ports timing parameters
15.17. TCM interface output ports timing parameters
15.18. FPU output port timing parameters
A.1. Global signals
A.2. Configuration signals
A.3. Interrupt signals
A.4. AXI master port signals for the L2 interface
A.5. AXI master port error detection signals
A.6. AXI slave port signals for the L2 interface
A.7. AXI slave port error detection signals
A.8. ATCM port signals
A.9. B0TCM port signals
A.10. B1TCM port signals
A.11. Dual core interface signals
A.12. Debug interface signals
A.13. Debug miscellaneous signals
A.14. ETM interface signals
A.15. Test signals
A.16. MBIST signals
A.17. Validation signals
A.18. FPU signals
C.1. Differences between issue B and issue C
C.2. Differences between issue C and issue D

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Revision History
Revision A15 May 2006First release for r0p1
Revision B22 October 2007First release for r1p2
Revision C16 June 2008First release for r1p3
Revision D11 September 2009Second release for r1p3
Revision E20 November 2009Documentation update for r1p3
Copyright © 2009 ARM Limited. All rights reserved.ARM DDI 0363E
Non-Confidential