Cortex-R4 and Cortex-R4F Technical Reference Manual: 9.3.1. Restrictions on AXI transfers

The Cortex-R4 AXI master interface applies the following restrictions to the AXI transactions it generates:

A burst never transfers more than 32 bytes.
The burst length is never more than 8 transfers.
No transaction ever crosses a 32-byte boundary in memory. See AXI transaction splitting.
FIXED bursts are never used.
The write address channel always issues INCR type bursts, and never WRAP or FIXED.
WRAP type read bursts, see Linefills:
- are used only for linefills (reads) of cacheable Normal non-shared memory
- always have a size of 64 bits, and a length of 4 transfers
- always have a start address that is 64-bit aligned.
If the transfer size is 8 bits or 16 bits then the burst length is always 1 transfer.
The transfer size is never greater than 64 bits, because it is a 64-bit AXI bus.
Instruction fetches, identified by ARPROT[2], are always a 64 bit transfer size, and never locked or exclusive.
Transactions to Device and Strongly-ordered memory are always to addresses that are aligned for the transfer size. See Strongly-ordered and Device transactions.
Exclusive and Locked accesses are always to addresses that are aligned for the transfer size.
Write data is never interleaved.
In addition, there are various limitations to the ID values that the AXI master interface uses. See Identifiers for AXI bus accesses.

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