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The processor reports the status and address of faults that occur during its operation. For both data and instruction faults there are two Fault Status Registers (FSRs) and one Fault Address Register (FAR).
Fields within the Data and Instruction FSRs indicate the priority and source of a fault and the validity of the address in the corresponding FAR. Table 4.27 shows this encoding for the FSRs.
Table 4.27. Fault Status Register encodings
| Priority | Sources | FSR [10,3:0] | FAR |
|---|---|---|---|
| Highest | Alignment | 0b00001 | Valid |
| Background | 0b00000 | Valid | |
| Permission | 0b01101 | Valid | |
| Synchronous External Abort | 0b01000 | Valid | |
| Asynchronous External Abort | 0b10110 | Unpredictable | |
| Synchronous Parity/ECC Error | 0b11001 | Valid | |
| Asynchronous Parity/ECC Error | 0b11000 | Unpredictable | |
| Lowest | Debug Event | 0b00010 | Unchanged |
All other encodings for these FSR bits are Reserved.
The DFSR characteristics are:
Holds status information regarding the source of the last data abort.
The DFSR is:
a read/write register
accessible in Privileged mode only.
Available in all processor configurations.
See Table 4.28.
Figure 4.30 shows the DFSR bit assignments.
Table 4.28 shows the DFSR bit assignments.
Table 4.28. DFSR Register bit assignments
Bits | Name | Function |
|---|---|---|
[31:13] | - | SBZ. |
[12] | SD | Distinguishes between an AXI Decode or Slave error on an external abort. This bit is only valid for external aborts. For all other aborts types of abort, this bit is set to zero:
|
[11] | RW | Indicates whether a read or write access caused an abort:
|
[10][a] | S | Part of the Status field. |
[9:8] | - | Always RAZ. Writes ignored. |
[7:4] | Domain | SBZ. This is because domains are not implemented in this processor. |
[3:0][a] | Status | Indicates the type of fault generated. To determine the data fault, you must use bit [12] and bit [10] in conjunction with bits [3:0]. |
[a] For more information on how these bits are used in reporting faults, see Table 4.27. | ||
To use the DFSR read or write CP15 with:
MRC p15, 0, <Rd>, c5, c0, 0 ; Read DFSR MCR p15, 0, <Rd>, c5, c0, 0 ; Write DFSR
The IFSR characteristics are:
Holds status information regarding the source of the last instruction abort.
The IFSR is:
a read/write register
accessible in Privileged mode only.
Available in all processor configurations.
See Table 4.29.
Figure 4.31 shows the IFSR bit assignments.
Table 4.29 shows the IFSR bit assignments.
Table 4.29. IFSR Register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:13] | - | SBZ. |
| [12] | SD | Distinguishes between an AXI Decode or Slave error on an external abort. This bit is only valid for external aborts. For all other aborts types of abort, this bit is set to zero:
|
| [11] | - | SBZ. |
| [10][a] | S | Part of the Status field. |
| [9:8] | - | SBZ. |
| [7:4] | Domain | SBZ. This is because domains are not implemented in this processor. |
| [3:0][a] | Status | Indicates the type of fault generated. To determine the instruction fault, bit [12] and bit [10] must be used in conjunction with bits [3:0]. |
[a] For more information on how these bits are used in reporting faults, see Table 4.27. | ||
To access the IFSR read or write CP15 with:
MRC p15, 0, <Rd>, c5, c0, 1 ; Read IFSR MCR p15, 0, <Rd>, c5, c0, 1 ; Write IFSR
The processor has two auxiliary fault status registers:
the Auxiliary Data Fault Status Register (ADFSR)
the Auxiliary Instruction Fault Status Register (AIFSR).
The auxiliary fault status registers characteristics are:
Provide additional information about data and instruction parity, ECC, and external TCM errors.
The auxiliary fault status registers are:
Read/write registers.
Accessible in Privileged mode only.
The contents of an auxiliary fault status register are only valid when the corresponding Data or Instruction Fault Status Register indicates that a parity or ECC error has occurred. At other times the contents of the auxiliary fault status registers are Unpredictable.
Available in all processor configurations.
See Table 4.30.
Figure 4.32 shows the auxiliary fault status register bit assignments.
Table 4.30 shows the auxiliary fault status register bit assignments.
Table 4.30. Auxiliary fault status register bit assignments
| Bits | Name | Function |
|---|---|---|
| [31:28] | - | SBZ. |
| [27:24] | CacheWay[a] | The value returned in this field indicates the cache way or ways in which the error occurred. |
| [23:22] | Side | The value returned in this field indicates the source of the error. Possible values are:
|
| [21] | Recoverable error | The value returned in this field indicates if the error is recoverable:
|
| [20:14] | - | SBZ. |
| [13:5] | Index[b] | This field returns the index value for the access giving the error. |
| [4:0] | - | SBZ. |
[a] This field is only valid for data cache store parity/ECC errors, otherwise it is Unpredictable. [b] This field is only valid for data cache store parity/ECC errors. On the AIFSR, and for TCM accesses, this field SBZ. | ||
To access the auxiliary fault status registers, read or write CP15 with:
MCR p15, 0, <Rd>, c5, c1, 0 ; Write ADFSR MRC p15, 0, <Rd>, c5, c1, 0 ; Read ADFSR MCR p15, 0, <Rd>, c5, c1, 1 ; Write AIFSR MRC p15, 0, <Rd>, c5, c1, 1 ; Read AIFSR
The DFAR characteristics are:
Holds the address of the fault when a synchronous abort occurs.
The DFAR is:
a read/write register
accessible in Privileged mode only.
Available in all processor configurations.
The DFAR bits [31:0] contain the address where the synchronous abort occurred.
To access the DFAR read or write CP15 with:
MRC p15, 0, <Rd>, c6, c0, 0 ; Read DFAR MCR p15, 0, <Rd>, c6, c0, 0 ; Write DFAR
A write to this register sets the DFAR to the value of the data written. This is useful for a debugger to restore the value of the DFAR.
The processor also updates the DFAR on debug exception entry because of watchpoints. See Effect of debug exceptions on CP15 registers and DBGWFAR for more information.
The IFAR characteristics are:
Holds the address of the instruction that caused a prefetch abort.
The IFAR is:
a read/write register
accessible in Privileged mode only.
Available in all processor configurations.
The IFAR bits [31:0] contain the Instruction Fault address.
To access the IFAR read or write CP15 with:
MRC p15, 0, <Rd>, c6, c0, 2 ; Read IFAR MCR p15, 0, <Rd>, c6, c0, 2 ; Write IFAR
A write to this register sets the IFAR to the value of the data written. This is useful for a debugger to restore the value of the IFAR.
| Copyright © 2006-2011 ARM Limited. All rights reserved. | ARM DDI 0363G |
| Non-Confidential | ID041111 |
| PDF version | |
| Home > System Control > Register descriptions > Fault Status and Address Registers |