12.3.8. APB port access permissions

The restrictions for accessing the APB slave port are described as follows:

Privilege of memory access

You must configure the system to disable accesses to the memory-mapped registers based on the privilege of the memory access.

Power down

The processor only supports a single power domain, therefore you must configure the system to return an error response to all accesses made to the APB interface while the processor is powered-down.

Privilege of memory access permission

When non-privileged software attempts to access the APB slave port, the system must ignore the access or generate an error response to the access. You must implement this restriction at the system level because the APB protocol does not have a privileged or user control signal. You can choose to have the system either ignore the access or generate an error response.

You can place additional restrictions on memory transactions that are permitted to access the APB port. However, ARM does not recommend this.

Locks permission

You can lock the APB slave port so that access to some debug registers is restricted. ARM architecture v7 defines two locks:

Software lock

The external debugger can set this lock to prevent software from modifying the debug registers settings. A debug monitor can also set this lock prior to returning control to the application to reduce the chance of erratic code changing the debug settings. When this lock is set, writes to all debug registers are ignored, except those generated by the external debugger, that override the lock. For more information, see Lock Access Register.

OS Lock

The processor does not support OS Lock.

Note

  • These locks are set to their reset values only on reset of the debug logic, provided by PRESETDBGn.

  • You must set the PADDRDBG31 input signal to 1 for accesses originated from the external debugger for the Software Lock override feature to work.

Table 12.4. External debug interface access permissions

  Registers
PADDRDBG31Lock

DBGDRCR, DBGPRCR, DBGPRSR

Other Debug registers

LAR

Other registers

XX[a]NPOSS[b]NPOSSbNPOSSbNPOSSb
1XaOK[c]OKcOKcOKc
01[d]WI[e]WIeOKcWIe
00OKcOKcOKcOKc

[a] X indicates that the outcome does not depend on this condition.

[b] Not possible. Accessing debug registers while the processor is powered down is not possible.

[c] OK indicates that the access succeeds.

[d] LSR[1] bit is set.

[e] WI indicates that writes are ignored.


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