Cortex-R4 and Cortex-R4F Technical Reference Manual: 12.5. Management registers

12.5. Management registers

The Management registers define the standardized set of registers that all CoreSight components implement. This section describes these registers.

Table 12.25 shows the contents of the Management registers for the processor debug unit.

Table 12.25. Management registers

Offset (hex)	Register number	Access	Mnemonic	Description
`0xD00-0xDFC`	832-895	R	-	Processor Identification Registers. See Processor ID Registers.
`0xF00`	960	RW	ITCTRL	Integration Mode Control Registers. See Integration Mode Control Register.
`0xFA0`	1000		CLAIMSET	Claim Tag Set Register. See Claim Tag Set Register.
`0xFA4`	1001		CLAIMCLR	Claim Tag Clear Register. See Claim Tag Clear Register .
`0xFB0`	1004	W	LOCKACCESS	Lock Access Register. See Lock Access Register.
`0xFB4`	1005	R	LOCKSTATUS	Lock Status Register. See Lock Status Register.
`0xFB8`	1006	R	AUTHSTATUS	Authentication Status Register. See Authentication Status Register.
`0xFB8-0xFC4`	1006-1009	R	-	Reserved.
`0xFC8`	1010	R	DEVID	Device Identifier. Reserved.
`0xFCC`	1011	R	DEVTYPE	Device Type Register. See Device Type Register.
`0xFD0-0xFFC`	1012-1023	R	-	Identification Registers. See Debug Identification Registers.

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