12.4.3. CP14 c0, Debug ROM Address Register

The DBGDRAR characteristics are:


Returns a 32-bit Debug ROM Address Register value. This is the address that indicates where in memory a debug monitor can locate the debug bus ROM specified by the CoreSight multiprocessor trace and debug architecture. This ROM holds information about all the components in the debug bus. You can configure the address read in this register during integration using the DBGROMADDR[31:12] and DBGROMADDRV inputs. DBGROMADDRV must be tied off to 1 if DBGROMADDR[31:12] is tied off to a valid value.

Usage constraints

The DBGDRAR Register is:

  • in CP14 c0, sub-register c1

  • a 32 bit read-only register

  • accessible in User and Privileged modes.


Available in all processor configurations.


Figure 12.3 shows the DBGDRAR bit assignments.

Figure 12.3. DBGDRAR Register bit assignments

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Table 12.8 shows the DBGDRAR bit assignments.

Table 12.8.  DBGDRAR Register bit assignments



Debug bus ROM address.

Indicates bits [31:12] of the debug bus ROM address.

[11: 2]




Valid bits

Indicates that the ROM address is valid.

Reads b11 if DBGROMADDRV is set to 1, otherwise reads b00. DBGROMADDRV must be set to 1 if DBGROMADDR[31:12] is set to a valid value.

To use the DBGDRAR Register, read CP14 c0 with:

MRC p14, 0, <Rd>, c1, c0, 0 ; Read DBGDRAR Register
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