3.7.6. Undefined instruction

When an Undefined instruction is encountered, or a VFP instruction, when the VFP is not enabled, the processor takes the Undefined Instruction exception. Software can use this mechanism to extend the ARM instruction set by emulating Undefined instructions. Undefined Instruction exceptions also occur when a UDIV or SDIV instruction is executed, when the value in Rm is zero and the DZ bit in the SCTLR is set.

If the handler is required to return after the instruction that caused the Undefined Instruction exception, it must:

IRQs are disabled when an Undefined instruction trap occurs. For more information about Undefined instructions, see the ARM Architecture Reference Manual.

Copyright © 2006-2011 ARM Limited. All rights reserved.ARM DDI 0363G
Non-ConfidentialID041111