4.3.12. c0, Current Cache Size Identification Register

The CCSIDR Register characteristics are:


Provides information about the size and behavior of the instruction or data cache. Architecturally, there can be up to eight levels of cache, containing instruction, data, or unified caches. This processor contains L1 instruction and data caches only. The CSSELR determines which CCSIDR to select, see c0, Cache Size Selection Register.

Usage constraints

The CCSIDR is:

  • a read-only register

  • accessible in Privileged mode only.


Available in all processor configurations.


Figure 4.23 shows the CCSIDR bit assignments.

Figure 4.23. CCSIDR Register bit assignments

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Table 4.19 shows the CCSIDR bit assignments.

Table 4.19. CCSIDR Register bit assignments


Name Function

Indicates support available for write-through:

1 = write-through support available[a]


Indicates support available for write-back:

1 = write-back support availablea


Indicates support available for read allocation:

1 = read allocation support availablea


Indicates support available for write allocation:

1 = write allocation support availablea


Indicates the number of sets as

(number of sets) - 1a


Indicates the number of ways as

(number of ways) - 1a

[2:0]LineSizeIndicates the number of words in each cache linea

[a] See Table 4.20 for valid bit field encodings.

The LineSize field is encoded as 2 less than log(2) of the number of words in the cache line. For example, a value of 0x0 indicates there are four words in a cache line, that is the minimum size for the cache. A value of 0x1 indicates there are eight words in a cache line.

Table 4.20 shows the individual bit field and complete register encodings for the CCSIDR. Use this to match the cache size and level of cache set by the CSSELR. See c0, Cache Size Selection Register.

Table 4.20. Bit field and register encodings for CCSIDR


Complete register encoding

Register bit field encoding

To access the CCSIDR read CP15 with:

MRC p15, 1, <Rd>, c0, c0, 0 ; Read CCSIDR
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