4.3.14. c0, Cache Size Selection Register

The CSSELR characteristics are:


Holds the value that the processor uses to select the CSSELR to use.

Usage constraints

The CSSELR is:

  • a read/write register

  • accessible in Privileged mode only.


Available in all processor configurations.


Figure 4.25 shows the CSSELR bit assignments.

Figure 4.25. CSSELR Register bit assignments

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Table 4.22 shows the CSSELR bit assignments.

Table 4.22. CSSELR Register bit assignments


[31: 4]-SBZ.

Identifies which cache level to select:

b000 = L1 cache

This field is read only, writes are ignored.


Identifies instruction or data cache to use:

1 = instruction

0 = data.

To access the CCSIDRs read or write CP15 with:

MRC p15, 2, <Rd>, c0, c0, 0 ; Read CSSELR
MCR p15, 2, <Rd>, c0, c0, 0 ; Write CSSELR
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