4.1.3. Cache control and configuration
The cache control and configuration registers:
provide information
on the size and architecture of the instruction and data caches
control cache maintenance operations that include
clean and invalidate caches, drain and flush buffers, and address
translation
override cache behavior during debug or interruptible
cache operations.
The cache control and configuration registers consist of three
read-only registers, one read/write register, and a number of write-only
registers. Figure 4.3 shows
the arrangement of the registers in this functional group.
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