4.3.30. Correctable Fault Location Register

The CFLR characteristics are:

Purpose

Indicates the location of the last correctable error that occurred during cache or TCM operations.

Usage constraints

The CFLR is:

  • a read/write register

  • accessible in Privileged mode only

  • not updated on:

    • speculative accesses, for example, an instruction fetch for an instruction that is not executed because of a previous branch

    • a TCM external error or external retry request.

  • updated on:

    • parity or ECC errors in the instruction cache

    • single-bit ECC errors in the data cache

    • parity or multi-bit errors in the data cache when write-through behavior is forced

    • single-bit TCM ECC errors.

  • updated by the processor, regardless of whether an abort is taken or an access is retried in response to the error.

Configurations

Available in all processor configurations.

Attributes

Every correctable error that causes a CFLR update also has an associated event. See Table 6.1 for the events that are related to CFLR updates. If two correctable errors occur simultaneously, for example an AXI slave error and an LSU or PFU error, the LSU or PFU write takes priority. If multiple errors occur, the value in the CFLR reflects the location of the latest event.

The same register is updated by all correctable errors. You can read bits [25:24] to determine whether the error was from a cache or TCM access.

Figure 4.52 shows the CFLR bit assignments, when it indicates a correctable cache error.

Figure 4.52. CFLR - cache, bit assignments

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Table 4.54 shows the CFLR bit assignments, when it indicates a correctable cache error.

Table 4.54. CFLR - cache, bit assignments

BitsNameFunction
[31:30]-RAZ
[29:26]WayIndicates the Way of the error.
[25:24]SideIndicates the source of the error. For cache errors, this value is always 0b00.
[23:14]-RAZ
[13:5]IndexIndicates the index of the location where the error occurred.
[4:2]-RAZ
[1:0]Type

Indicates the type of access that caused the error:

0b00 = Instruction cache.

0b01 = Data cache.


Figure 4.53 shows the CFLR bit assignments, when it indicates a correctable TCM error.

Figure 4.53. CFLR - TCM, bit assignments

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Table 4.55 shows the CFLR bit assignments, when it indicates a correctable TCM error.

Table 4.55. CFLR - TCM, bit assignments

BitsNameFunction
[31:26]-RAZ
[25:24]Side

Indicates the source of the error:

0b01 = ATCM

0b10 = BTCM

[23]-RAZ
[22:3]AddressIndicates the address in the TCM where the error occurred.
[2]-RAZ
[1:0]Type

Indicates the type of access that caused the error:

0b00 = Instruction.

0b01 = Data.

0b10 = AXI slave

0b11 is unused.


To access the CFLR, read or write CP15 with:

MRC p15, 0, <Rd>, c15, c3, 0 : Read CFLR
MCR p15, 0, <Rd>, c15, c3, 0 : Write CFLR
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