4.3.13. c0, Current Cache Level ID Register

The CLIDR Register characteristics are:

Purpose
  • Indicates the cache levels that are implemented. Architecturally, there can be a different number of cache levels on the instruction and data side.

  • Captures the point-of-coherency.

  • Captures the point-of-unification.

Usage constraints

The CLIDR is:

  • a read-only register

  • accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

Figure 4.24 shows the CLIDR bit assignments.

Figure 4.24. CLIDR Register bit assignments

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Table 4.21 shows the CLIDR bit assignments.

Table 4.21. CLIDR Register bit assignments

Bits Name Function
[31:30]-SBZ
[29:27]LoU

Level of Unification:

0b001 = L2, if either cache is implemented

0b000 = L1, if neither instruction nor data cache is implemented.

[26:24]LoC

Level of Coherency:

0b001 = L2, if either cache is implemented

0b000 = L1, if neither instruction nor data cache is implemented.

[23:21]CL 80b000 = no cache at Cache Level (CL) 8
[20:18]CL 70b000 = no cache at CL 7
[17:15]CL 60b000 = no cache at CL 6
[14:12]CL 50b000 = no cache at CL 5
[11:9]CL 40b000 = no cache at CL 4
[8:6]CL 30b000 = no cache at CL 3
[5:3]CL 20b000 = no cache at CL 2
[2]CL 1RAZ. Indicates no unified cache at CL1
[1]CL 1

0b000 = no data cache is implemented

0b001 = data cache is implemented.

[0]CL 1

0b000 = no instruction cache is implemented.

0b001 = an instruction cache is implemented.


To access the CLIDR, read CP15 with:

MRC p15, 1, <Rd>, c0, c0, 1 ; Read CLIDR
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