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Home > System Control > Register descriptions > c0, Current Cache Level ID Register |
The CLIDR Register characteristics are:
Indicates the cache levels that are implemented. Architecturally, there can be a different number of cache levels on the instruction and data side.
Captures the point-of-coherency.
Captures the point-of-unification.
The CLIDR is:
a read-only register
accessible in Privileged mode only.
Available in all processor configurations.
See Table 4.21.
Figure 4.24 shows the CLIDR bit assignments.
Table 4.21 shows the CLIDR bit assignments.
Table 4.21. CLIDR Register bit assignments
Bits | Name | Function |
---|---|---|
[31:30] | - | SBZ |
[29:27] | LoU | Level of Unification:
|
[26:24] | LoC | Level of Coherency:
|
[23:21] | CL 8 | 0b000 = no cache at Cache
Level (CL) 8 |
[20:18] | CL 7 | 0b000 = no cache at CL 7 |
[17:15] | CL 6 | 0b000 = no cache at CL 6 |
[14:12] | CL 5 | 0b000 = no cache at CL 5 |
[11:9] | CL 4 | 0b000 = no cache at CL 4 |
[8:6] | CL 3 | 0b000 = no cache at CL 3 |
[5:3] | CL 2 | 0b000 = no cache at CL 2 |
[2] | CL 1 | RAZ. Indicates no unified cache at CL1 |
[1] | CL 1 |
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[0] | CL 1 |
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To access the CLIDR, read CP15 with:
MRC p15, 1, <Rd>, c0, c0, 1 ; Read CLIDR