4.3.3. c0, Cache Type Register

The CTR characteristics are:

Purpose

Determines the instruction and data minimum line length in bytes, to enable a range of addresses to be invalidated.

Usage constraints

The CTR is:

  • a read-only register

  • accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

Figure 4.8 shows the CTR bit assignments.

Figure 4.8. CTR Register bit assignments

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Table 4.4 shows the CTR bit assignments.

Table 4.4. CTR Register bit assignments

Bits

Name

Function

[31:28]

-Always b1000.
[27:24]CWG

Cache Write-back Granule:

0x0 = no information provided. See maximum cache line size in c0, Current Cache Size Identification Register.

[23:20]ERG

Exclusives Reservation Granule:

0x0 = no information provided.

[19:16]DMinLine

Indicates log2 of the number of words in the smallest cache line of the data and unified caches controlled by the processor:

0x3 = eight words in an L1 data cache line.

[15:14]-

Always 0x3.

[13: 4]-Always 0x000.
[3: 0]IMinLine

Indicates log2 of the number of words in the smallest cache line of the instruction caches controlled by the processor:

0x3 = eight words in an L1 instruction cache line.


To access the CTR, read CP15 with:

MRC p15, 0, <Rd>, c0, c0, 1 ; Read CTR
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