6.3.10. c9, User Enable Register

The PMUSERENR Register characteristics are:


Enables User mode to have access to:

Usage constraints

The PMUSERENR Register:

  • is a read/write register

  • is writable only in Privileged mode, readable in any processor mode

  • does not provide access to the registers that control interrupt generation.


Available in all processor configurations.


Figure 6.8 shows the PMUSERENR bit assignments.

Figure 6.8. PMUSERENR Register bit assignments

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Table 6.9 shows the PMUSERENR bit assignments.

Table 6.9. PMUSERENR Register bit assignments


[31:1]-RAZ or SBZP.

User mode access to performance monitor and validation registers:

0 = Disabled. This is the reset value.

1 = Enabled.

If the EN bit in the PMUSERENR register is not set, any attempt to access a performance monitor register or a validation register from User mode causes an Undefined Instruction exception.


For more information on access permissions to the performance monitor registers and validation registers, see the ARM Architecture Reference Manual.

To access the PMUSERENR register, read or write CP15 with:

MRC p15, 0, <Rd>, c9, c14, 0 ; Read  PMUSERENR Register
MCR p15, 0, <Rd>, c9, c14, 0 ; Write PMUSERENR Register
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