Cortex-R4 and Cortex-R4F Technical Reference Manual: 6.3.11. c9, Interrupt Enable Set Register

6.3.11. c9, Interrupt Enable Set Register

The PMINTENSET Register characteristics are:

Purpose

Determines if any of the PMXEVCNTR Registers, PMXEVCNTR0-PMXEVCNTR2 and PMCCNTR, generate an interrupt request on overflow.

Usage constraints

The PMINTENSET Register is:

a read/write register
accessible in Privileged mode only.

Configurations

Available in all processor configurations.

Attributes

See Table 6.10.

Figure 6.9 shows the PMINTENSET bit assignments.

Figure 6.9. PMINTENSET Register bit assignments

Table 6.10 shows the PMINTENSET bit assignments.

Table 6.10. PMINTENSET Register bit assignments

Bits	Name	Function
[31]	C	PMCCNTR overflow interrupt
[30:3]	-	UNP on reads, SBZP on write
[2]	P2	PMC2 overflow interrupt
[1]	P1	PMC1 overflow interrupt
[0]	P0	PMC0 overflow interrupt

Reading this register returns the current setting, with a 1 in one of the counter bits indicating that interrupts are enabled for that counter. Writing a 1 to a particular interrupt bit enables interrupt generation on overflow of that counter. Writing a 0 has no effect. You can only disable interrupts by writing to the PMINTENCLR Register.

To access the PMINTENSET Register, read or write CP15 with:

MRC p15, 0, <Rd>, c9, c14, 1 ; Read  PMINTENSET Register
MCR p15, 0, <Rd>, c9, c14, 1 ; Write PMINTENSET Register

If this unit generates an interrupt, the processor asserts the pin nPMUIRQ. You can route this pin to an external interrupt controller for prioritization and masking. This is the only mechanism that signals this interrupt to the processor.

Note

ARM expects that the Performance Monitor interrupt request signal, nPMUIRQ, connects to a system interrupt controller.

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