4.3.18. c1, Coprocessor Access Register

The CPACR characteristics are:

Purpose

Sets access rights for coprocessors.

Usage constraints

The CPACR is:

  • A read/write register.

  • Accessible in Privileged mode only.

  • Because this processor does not support coprocessors CP0-CP9, CP12, and CP13, bits [27:24] and [19:0] in this register are read-as-zero and ignore writes.

  • CPACR has no effect on access to CP14, the debug control coprocessor, or CP15, the system control coprocessor. The only other coprocessor that the Cortex-R4F processor includes is the FPU, CP10, and CP11. This register enables software to determine if the FPU exists in the processor.

Configurations

Available in all processor configurations.

Attributes

Figure 4.29 shows the CPACR bit assignments.

Figure 4.29. CPACR Register bit assignments

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Table 4.26 shows the CPACR bit assignments.

Table 4.26. CPACR Register bit assignments

Bits

Name Function
[31:28]-SBZ.
[27:0]cp<n>[a]

Defines access permissions for each coprocessor

Access denied is the reset condition, and is the behavior for non-existent coprocessors:

b00 = Access denied. Attempts to access generates an Undefined Instruction exception.

b01 = Privileged mode access only

b10 = Reserved

b11 = Privileged and User mode access.

Access permissions for the FPU are set by fields cp10 and cp11. For all other coprocessor fields, the value is fixed to b00.

[a] n is the coprocessor number between 0 and 13.


To access the CPACR, read or write CP15 with:

MRC p15, 0, <Rd>, c1, c0, 2 ; Read CPACR
MCR p15, 0, <Rd>, c1, c0, 2 ; Write CPACR
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