2.3.3. Clocking

The processor has two functional clock inputs. Externally to the processor, you must connect together CLKIN and FREECLKIN.

In addition, there is the PCLKDBG clock for the debug APB bus. This is asynchronous to the main clock.

All clocks can be stopped indefinitely without loss of state.

Three additional clock inputs, CLKIN2, DUALCLKIN, and DUALCLKIN2, are related to the dual-redundant core functionality, if included. If you are integrating a Cortex-R4 macrocell with dual-redundant core, contact the implementer of that macrocell for information about how to connect the clock inputs.

The following is described in this section:

AMBA interface clocking

The AXI master and slave interfaces must be connected to AXI systems that are synchronous to the processor clock, CLKIN, even if this might be at a lower frequency. This means that every rising edge on the AXI system clock must be synchronous to a rising edge on CLKIN.

The AXI master interface clock enable signal ACLKENM and the AXI slave interface clock enable signal ACLKENS must be asserted on every CLKIN rising edge for which there is a simultaneous rising edge on the AXI system clock.

Figure 2.3 shows an example in which the processor is clocked at 400MHz (CLKIN), while the AXI system connected to the AXI master interface is clocked at 200MHz (ACLKM). The ACLKENM clock indicates the relationship between the two clocks.

Figure 2.3. AXI interface clocking

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If the AMBA system connected to an interface is clocked at the same frequency as the processor, then the corresponding clock enable signal must be tied HIGH.

Clock gating

In Standby mode the processor can gate its own clock to save power. See Chapter 10 Power Control for more information about Standby mode. You can use the STANDBYWFI output to gate the clock to the TCMs when the processor is gating its own clock in Standby mode. If you do, you must design the logic so that the TCM clock starts running within four cycles of STANDBYWFI going LOW.

Figure 2.4 shows an example of an ATCM access occurring immediately after the processor exits Standby mode. STANDBYWFI indicates when the processor internal clock, shown as CPU_CLK, is restarted. The clock to the ATCM, shown as ATCM_CLK, is gated off in Standby mode. It is restarted by the third cycle to enable the ATCM to assert ATCEN0 in response to the access that the processor presents. This example shows the worst-case, that is, the earliest TCM access that the processor can generate after exiting Standby mode.

Figure 2.4. Standby, wake-up

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