This section describes the main components of the processor:
Figure 2.1 shows the structure
of the processor.
The PreFetch Unit (PFU) fetches instructions
from the memory system, predicts branches, and passes instructions
to the Data Processing Unit (DPU). The DPU
executes all instructions and uses the Load/Store Unit (LSU)
for data memory transfers. The PFU and LSU interface to the L1 memory
system that contains L1 instruction and data caches and an interface
to a L2 system. The L1 memory can also contain optional TCM interfaces.
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